Brand new user here, couple of years Eagle experience, first KiCad project. I’m using KiCad 7.0.9, default install, Windows 11.
When routing tracks between two ICs, the first two tracks went all the way to the pads while the second and subsequent tracks stopped just short of the pad and won’t connect. I am not sure why.
I wonder if the default track width is too thick for the pad pitch on the second IC.
the thin lines around the pins that overlaps the adjacent pin, is telling you that a constrain value is too high, so the connection is not possible without braking the design rule.
You have to check the constrain values and net classes for the design from here:
Many thanks for the pointers! I was able to add a new “Thin” value and assign it to netclasses used on the narrower pitch IC.
One downside is that the power netclasses (5V, GND) now use those narrower tracks. My plan is to make a “wide” value, assigned to those netclasses, and hope I get to choose which one to use when routing.
If one of the posts is a clear solution to your problem, then get into the habit of clicking on the Solution button.
For a simple and short topic like this it does not matter much, but for longer threads it helps other who are searching the forum for answers to find what they want quicker. It’s good to make a habit out of this.
Thanks for the hint. It solved the original problem but introduced another.
Should I continue in that thread until it is all solved, or mark it solved and start a new thread (most forums frown on spamming threads for closely related topics).
Happy to follow whatever are the conventions here.
If you feel it isn’t ‘close enough’, please start a new thread if the contents of the above become irrelevant to the new problem. It keeps searching solutions easier. Thanks for asking.
It’s still related to the same topic, in fact it is the same thing: problems with clearances.
In the green encircled areas, the clearance line of one net is overlapping with a pad of another net, and this is always a DRC violation. Clearances can overlap with each other, but a clearance line may never touch the copper of another net.
There are two ways to fix it. Either make the clearance smaller, or make the pads narrower.
Also from your (extremely big) screenshot. (I assume you have got such a new fangled monitor with very tiny pixels.)
Using such small clearances and track width is getting into the area that your PCB becomes more difficult to manufacture (and thus more expensive). It’s difficult to get some scale from your screenshot, but it looks like your footprint has a 0.5mm or 0.6mm pitch, and the pads are wider then the clearance. What is the origin of this footprint? It is more common to use narrower pads to leave more room for the clearance.
Thanks for the hint, best to discover at this stage rather than getting unusable PCBs back from the fab!
The part with the fine-pitch pads is a TI DAC8168 octal-channel 14-bit DAC. It comes in a TSSOP-16 package, which according to the DAC8168 data sheet has a 0.65mm pitch. I ordered it from Mouser, and since KiCad did not have that part I downloaded the ECAD package from the Mouser page and converted it to KiCad using the Library Loader tool. This claimed to make symbols, 3D models and footprints.
The symbol worked fine, but switching to PCB said there was no footprint. So in the schematic editor, I gave the symbol a default footprint, selecting from the KiCad stock library … aaand now I see the problem. I had picked
Package_SO:TSSOP-16_4.4x3.6mm_P0.4mm
without noticing that _P0.4mm on the end. So it is the wrong footprint. There is also
Package_SO:TSSOP-16_4.4x5mm_P0.65mm
which I just updated to. And now the PCB has the larger footprint. Thanks for saving me from an unusable PCB!
I was unaware that TSSOP came in two different pin pitches. And the default window size for selecting footprints does not display the whole string.
There are lots of small details for footprints. Similar packages can have different pitch, but also different widths, and the pinout of IC’s may change with different packages. You should always do a verification step of all footprints, schematic symbols and other things before final ordering of the PCB.
svgeesus
The problem of overlapping is not necessarily a problem of the TRACE. In your original post, the adjacent PINS were closer spaced than the limit. You may have to reduce a global spacing in order to not have footprint pins violating the rules, then the Trace will work.
He already wrote he accidentally used a footprint with a 0.4mm pitch instead of 0.65mm. With the extra 0.25mm he already has plenty of clearance.
It’s a bit weird how big a quarter of a mm is sometimes.
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