[SOLVED] SPICE Netlist Does Not Match Schematic (actually it's user error in EESchema)


#1

I’m not sure if this is operator error on my part (likely) or a bug (unlikely). From what I can tell the Netlist KiCad is producing does not match the visual schematics that KiCad is showing me.

I am a newb, and am working on a learning project. My current work in progress is here: GitHub That directory is a flat structure of many sheets. This is probably not the best organizational scheme but it’s got a very low barrier to entry. Learning how to better manage these kinds of things is another question for another day.

In this directory there is a schematic called alu-test.sch (can’t link as a newb), it consumes many sheets. alu-test.cir is the outputted netlist.

What’s stumping me are lines 542, and 578: “R372 /alu/Vcc /alu/AdderS1 1K” this part makes sense, a little later in the file “R399 /alu/Vcc /alu/AdderS1 1K” the line is repeated.

Based on the schematic I would have expected the second line to have read AdderS2 as opposed to AdderS1

In the above picture the lines AdderS1 and AdderS2 are distinctly separate. Obviously they could end up being common if adder-4 or mux-4-4-1 connect the wires but as far as I can tell both sheets treat the wires independently.

What’s bugging me is that I have tested both the adder-4 and the mux-4-4-1 in isolation and they seem to work fine. For example adder-4 has four distinct output bits (adder-4-test.cir) and mux-4-4-1 has distinct input bits (multiplexer-4-4-1-test.cir) I’m not sure if there’s some obvious KiCad thing I’m missing here :confused:

Also I am cross posting as this forum seems like a better space for my question than the KiCad Q/A section in their bug tracker If I should close the other question I’d be happy to.


#2

Check with the highlight net tool if kicad sees these two nets as separate or as independent.


#3

That sounds like a great idea. Is that possible in EESchema? The references I’ve seen so far point to PCBNew.

(I am running KiCad 5.0.1)


#4

Highlight for schematic was introduced with version 5. Look in the right toolbar of eeschema :wink:


#5

Thanks. I am not sure how I missed that icon! Hopefully I missed something equally obvious in the schematic. The highlighting certainly helps but I’m still not seeing where I’ve gone wrong.

I’m wondering if I’ve somehow used a global label instead of hierarchical, or something not-too obvious that a newb like me would miss.

Unfortunately as a new user I’m only allowed to upload one image… diving through these sheets is a bit more intensive.

I did a screen recording instead, it was recorded at full resolution but YouTube’s compression is a bit agressive: https://www.youtube.com/watch?v=bSrkcxMrGHY&feature=youtu.be

Thanks in advance!


#6

You have a wire connecting the pins A1 and A2. (Sorry i missed that the last time around.)


#7

Amazing! I might need to go get my eyes checked. Thanks for all your help!


#8

In Pcbnew there are net ties to connect 2 nets together.
Having something similar in Eeschema seems like a good idea, in combination with generating ERC errors if a wire has 2 different labels.

I’m also not sure what happens with “Cout” as both a hierarchical and local label.