I’ve created a new footprint (PL2) by merging a SMT and THT footprint together. I’m using this on a 4 layer board, where the outer layers and one inner layer have a Ground pour across the entire layer. The other inner layer has a +5v copper pour across its entire layer. The issue I have is that when one of the PL2 THT pads is connected to GND, the entire outer layers get flooded with copper, obliterating any other tracks on that layer. If I attach a different net to the THT pad, the flood works correctly with the correct spacing between the various tracks and the Ground pour.
PL2 THT Pad 3 attached to GND. No copper pour shown:
Actually, I think there may still be a residual bug here? The Thermal Relief gap setting still seems to be getting ignored.
The final picture in my first post shows several GND pads on the RHS with the appropriate gap. These gaps don’t exist in the picture on my second post, which was done on v7.0.7.
On some KiCad related website I read they expect there are still a bunch of residual bugs in that “Clipper2” library, and this may come back and need some more debugging effort in the future. But the usual problem is that it is very difficult to find bugs if you can’t trigger them somehow.
The good news though, is that a bug like this got fixed in two days after reporting. Finding an reporting bugs with test cases is an excellent way in which all “regular” KiCad users can help the developers. Developers are a very scarce resource for KiCad (there are 1400 issues open on Gitlab, and a few hundred of those are wishlisht items for new features). And when users spend some time in finding, analyzing and reporting bugs, then the developers have more time left over for actually writing code and fixing the bugs.
In my defence, the PL2 footprint was initially a SMT only part, hence the original routing on the top layer. I then adapted the footprint by adding in a row of PTHs (I actually merged two footprints together) and then just lazily adjusted the already routed tracks! I then got distracted with the copper flood issue, so never really noticed the sub optimal track routing. I’ve now updated the board, and routed those tracks on the bottom layer, as per your suggestion.
When this thread wonders off towards ground plane design instead of KiCad bugs…
The current design is… atrocious. There just is not anything resembling a decent GND plane. On the level of RaptorUK’s suggeston, you can do a lot more. Ideally, there should not be any tracks at all on a good GND plane. But on a 2 layer PCB that is often difficult to achieve, but still you should strive to get as close as that as possible. There should never any gap in the GND plane that is bigger then a handful of mm. A 3mm gap is better then a 5mm gap. There are good reasons behind this, and you clearly have not given much thought about this yet. There are a bunch of very good youtube tutorials about GND planes and their importance to design them properly. Especially the Rick Hartley video is Highly recommended to watch (it’s from that other PCB design suite thingy) That video is (just) over two hours long, but it is worth watching.
But that said. GND planes are not always used. I am now working on a headphone amplifier kit, and It’s PCB uses mostly star grounding, combined with some other layout tricks to separate high current GND paths from signal GND paths, and this is a totally different approach and adequate for low speed analog design. But when dealing with digital signals and short rise and fall times, a decently designed GND plane becomes important, but also dependent on the technology used. Slow 8-bit uC’s and “old fashioned” logic are fairly tolerant, but for more modern electronics with steeper switching flanks, a good GND plane becomes mandatory. And especially when it is a commercial product and has to comply with EMC rules.
I take exception to that! I did say that this was a 4 layer board and that one of the inner layers also had a GND pour. There is nothing else on that layer.
