[SOLVED] ERC: Everything is complaining of missing Simulation models

Why is this happening? BUG?

Application: KiCad Schematic Editor x86_64 on x86_64

Version: 7.0.2-unknown-202305101703~2066af9f28~ubuntu23.04.1, release build

	wxWidgets 3.2.2
	FreeType 2.12.1
	HarfBuzz 6.0.0
	FontConfig 2.14.1
	libcurl/7.88.1 OpenSSL/3.0.8 zlib/1.2.13 brotli/1.0.9 zstd/1.5.4 libidn2/2.3.3 libpsl/0.21.2 (+libidn2/2.3.3) libssh/0.10.4/openssl/zlib nghttp2/1.52.0 librtmp/2.3

Platform: Ubuntu 23.04, 64 bit, Little endian, wxGTK, ubuntu-xorg, x11

Build Info:
	Date: May 10 2023 17:03:48
	wxWidgets: 3.2.2 (wchar_t,wx containers) GTK+ 3.24
	Boost: 1.74.0
	OCC: 7.6.3
	Curl: 7.88.1
	ngspice: 38
	Compiler: GCC 12.2.0 with C++ ABI 1017

Build settings:

No bug, only unpleasant default setting.
At some time a ERC-check was introduced to check if a symbol also contains a simulation model. Useful for the people who use the simulation-feature.
Sadly this ERC-check was added with violation-severity set to error.

Just switch off this check:
schematic setup–>Electrical Rules–>Violation Severity–>section miscellaneous–>SPICE model issue

Setting will be saved with your project (so maybe you have to do this for multiple projects).

Definitely useful. But ERC could have some checkboxes to disable some things, maybe.

ah, now we are talking, thanks. I could not find this without you.

additional hint:
if you right-click on a ERC/DRC-error-headline you get a context-menu where you individually can change this specific error-type (see picture).

disadvantage for the first time: you still don’t know how the specific error-check is named in the preferences-severity dialog.

A visible checkbox in that window would make more sense, in this case.

Kicad is essentially a tool for making PCBs, it was later considered interesting for simulation since Kicad schematics are a good visible way to handle circuits instead of text files only.

Most of the time, and since the Kicad does not have a Simulation lib built in, the simulation is just an alternative use of Kicad. So I understand that the simulation check should not disrupt its use in the first place, especially when making the ERC.

But a visible checkbox that is unchecked by default. Could be a good solution.

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