I am developing a logic level tester that is capable of telling a rising/falling edge of the signal in addition to the logical “1” and “0”.
In the circuit below, U1C is connected in a “data slicer” fashion and works well for the falling edge, as the voltage difference between its inputs is negative.
However, the rising edge is hardly detected as the yellow LED stays off due to the positive voltage difference on U1C, see the plot below. In the plot below: green = VPROBE; red = I_d (YELLOW_LED).
Basically, how do I make it work for both rising and falling edges? Can somehow ensure the output of U1C is always V- if there is a difference on the inputs?
BTW, many thanks to @BobZ, @paulvdh and @radix for their previous input on this one.