Hello!
I am developing a logic level tester that is capable of telling a rising/falling edge of the signal in addition to the logical “1” and “0”.
In the circuit below, U1C is connected in a “data slicer” fashion and works well for the falling edge, as the voltage difference between its inputs is negative.
However, the rising edge is hardly detected as the yellow LED stays off due to the positive voltage difference on U1C, see the plot below. In the plot below: green = VPROBE; red = I_d (YELLOW_LED).
Basically, how do I make it work for both rising and falling edges? Can somehow ensure the output of U1C is always V- if there is a difference on the inputs?
BTW, many thanks to @BobZ, @paulvdh and @radix for their previous input on this one.
I think you intended to use U1D as a buffer, as I suggested in the previous thread…
If so, then swap pins 12 and 13.
For simulation it does not matter much what the value of R1 is. In a real world application I would increase it a lot, probably 100k or more, to be able to withstand over voltages and ESD events better. Depending on what sort of offset is tolerable. And you may want to add a pulldown for when your logic probe is not connected. The bias input current of an opamp is small, but it has to go somewhere. For proper operation each opamp input needs a DC path for the bias current.
For pin 10, this path is through R2 & R5 because the capacitors do not let DC through.
For your pulse forming circuit…
I don’t know. You are the one with a working spice simulation of your circuit, and the motivation to spend time on it. So poke around those R’s and C’s and measure how your pulse shaping circuit is (mis) behaving.
Thanks for the tips!
However, regarding the edge detection circuit I have a comment: it is unfortunate that adjusting RC parameters do not really allow me to achieve this, see the plot below.
I do not know a simple circuit that would make all those pulses negative. That is the problem.
Potential solution: an RC-circuit for edge detection. It works, but produces a sharp spikes in LED current. Also, due to the nature of the LEDs, I need two of them to account for both rising and falling edges.
I still think the input needs to go via an op-amp buffer first of all. Sticking a 1k load on the circuit under test will very often totally alter its behaviour.
The input impedance of that logic level tester would be much better at around 10M, not 1k.
At: SteveT
The 100K resistor from the latest iteration does not set the input impedance. I is just a “current limiting” and over voltage protection resistor.
For Breezerider:
If you really want to build this circuit then the bias current of the U1D has nowhere to go when your test lead is hanging loose. It is common to use a high value resistor to GND to give the bias current a path to GND, and then this also sets the input impedance.
U1C is connected improperly here. Shorting all the wires together and to GND is not good. (Neither is leaving the inputs open). Check the datasheet or AN for the proper way to passivate an unused opamp.
Finally, I arrived at the design below. Transistors Q1 & Q2 come from [1]. The edge detection circuit works well for pulses over 33 V/s, but one may achieve lower values by tweaking values of C1,2. However, it does not seem easy to implement this in an actual circuit.
Thank you for proposing such an interesting design as well going in detailed on it’s inner workings! The simulation software looks nice too.
While I also considered such design myself, but I had to give it up. I got worried that the small voltage differences may cause the diodes to switch very fast between open and closed state leading to jitter. And this was the technical reason I considered a design which could be operated by very small currents, i.e., involving transistors (see below).
Your simulation output looks quite good, and your schematic also looks quite neat for what it does.
I also see you put a “1mega” resistor R2 in the input, but it’s on the wrong input
For simulation it won’t matter. the goal is (still) to have a DC path for the bias current on pin 12 of the LM324. When VTEST is open that bias current has nowhere to go. (I assume it is a probe you have to put into some circuit under test)
