[SOLVED] Difference in copper pour between V6 and V7?

I installed V7 today and opened a small V6 project. All looks good, apart from the copper pours around the mounting holes.

These zones are isolated and meant to save some etching. In V6 the zone uses the clearance around the mounting holes, while V7 pours right up to the mounting hole. Looking at V6 and V7 side-by-side I do not see any difference in the properties, which makes me wonder, did something change there or is a setting somewhere else controlling this?

Can you upload the project?

Can you make a (small) screenshot of each version around the mounting hole? I don’t understand it from the text alone.

Which versions do you have? (a bit more information than just V6 and V7)


V6.0.11, V7.0.8

copper to edge clearance? maybe it was differently implemented in 6.xx…


Apperently not

Edit: But you don’t need to do that anymore. Was able to replicate it.

It looks like KiCad 7 ignores “Abstandsmass” (not sure about the english term) in the copper pour settings for holes that are manually drawn (instead of NPTH) with Edge.Cuts.
In KiCad you can set it by settings the Copper to edge clearance of the board. If you want that clearance for only the copper pour and not for tracks, you may have to use custom rules.

(Too late, but 1920x1049 isn’t exactly small for a screenshot)

Very likely that this can solve it, but it doesn’t explain it. If this wasn’t implemented in version 6 but in 7, then you would expect the behaviour the other way around.
Edit: It was already implemented in version 6.

copper to edge clearance

most likely.
If I recall correctly v6 used the zone-copper-clearance as distance to holes/board edges (for zone fill).

While for v7 onwards the zone fill relies on the global copper-to-edge clearance value.

Tested it: version 6 check for that clearance, but it also checks for the copper to edge clearance and uses the larger one of them.

It would have helped if you uploaded the project as jhoannespfister asked, but I spend some 10 minutes to create a similar dummy project:

As you can see, there are different clearances for the PCB edge and around the hole.
You can set these clearances in: PCB Editor / File / Board Setup / Design Rules / Constraints as the Copper to hole clearance (I set it from default 0.25mm to 1mm) and the Copper to edge clearance (Which is Zero by default, and I set this to 2.5mm).

In my test project KiCad sets these two clearances independent of each other.

2023-10-05_asdf_hole_clearance.zip (12.3 KB)

Thanks, I learned something today. The default copper to edge clearance was set to 0 in both instances, but in V7 it used it apparently. Setting it to .8mm gave me the same result as I had in V6.

About the upload of an example, I reasoned that this screenshot was the quickest way to show the ‘problem’ while showing the properties of the zones at the same time. In this day and age a 1 Mb file is not that large. But if that is a nono I won’t do it again. :slightly_smiling_face:

A screenshot is just pixels, and you can’t look into the structure of the project.
With the project itself, you can open it in KiCad, see how it’s made and look at the project settings, etc.

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