[SOLVED]Bus graphically connected but is not a member of that bus

[Sprig]

In the ERC report:

[net_not_bus_member]: Net /r1 is graphically connected to bus / but is not a member of that bus;

Not certain why this became an issue when migrating from 5 to 6. What is the most common way to fix this?

[craftyjon]

It will be hard to advise without a screenshot of your design showing the location of the error.

The way to fix this is as the ERC says: make sure a net that is connected to a bus is actually a member of that bus.

[ML9104]

The bus thing changed from 5 to 6.
Your bus should now always have a label that contains the bus members. Either as, eg, Busname[0…12], or explicitly using curly brackets.

[Sprig]

@craftyjon

…without a screenshot of your design showing the location of the error.

Well, the arrow locations keep moving around; or I would have.

@craftyjon

make sure a net that is connected to a bus is actually a member of that bus.

Okay, I will re-create a proper V6 bus.

Thanks to both of you!

[Piotr]

@ML9104

Your bus should now always have a label that contains the bus members.

What a pity that wire entry to bus is not 1/2 size.
Because of this I use one bus for all signals going out of microcontroller even they are separate groups going to different ICs.
So it looks that if I were using ERC I would be expected to list all:
RST, INT, CS, SCK, SO, SI - signals to Wiznet W5500,
RXD, TEN, TXD - signals to RS485,
FCS, FCK, FSI, FSO, FRST - signals to flash memory
… and more (EEPROM, RTC),
in one bus description.
Don’t you think wire to bus entry could have two sizes to be selected from?

[Gracana]

Because of this I use one bus for all signals going out of microcontroller even they are separate groups going to different ICs.

If you put those signals into one or multiple aliases, you can then write your bus label using the short alias names.

[Piotr]

@Gracana

If you put those signals into one or multiple aliases

I don’t understand, but I don’t ask for explanation.
Till now aliases in KiCad context for me were only symbol aliases (in V5).
I don’t plan to complicate the signal name subject with adding something extra to them (I suppose that you suggest to duplicate each signal name by giving it the second name).

[Gracana]

Oh no, I wouldn’t suggest you do that. Bus aliases allow you to name a whole group of members. You could have an alias “MCU” contain all the of the microcontroller signals, then your bus label is just “{MCU}” rather than a long list.

[craftyjon]

You can also turn off this ERC in Schematic Setup if you don’t care about it. It sounds like you are using buses just as graphical “candy” and not electrical connections.

[Piotr]

@craftyjon

You can also turn off this ERC in Schematic Setup if you don’t care about it. It sounds like you are using buses just as graphical “candy” and not electrical connections.

I am designing my first V6 PCB (I don’t count very small one (pen-drive size) I have done half year ago spending on it few hours). And you are right - I use buses as graphic only.
I responded in this thread only because when I read that you should list at bus all signals in it I thought that if there were less of these signals in the bass, it would be easier. And if bus entry could be 1/2 size you will be able (having microcontroller pins with standard distance) to have several buses vertically in paralel to put each pin into bus you want and then at horizontal part of each bus list signals in it.

I need not to turn anything in ERC off as I don’t use ERC at all (never even tried to run it).
In past (V5) whenever I sow here the question about lacking of Power output pin at net with Power Input pins (in my opinion that checking generates much more noise here than helps to avoid bugs) I added my suggestion that instead of litter schematic with PWR_FLAGS you can also just not run ERC.
But I was scolded that this is bad advice and I stopped to do that anymore.
As I start to use V6 I don’t know it well but I know that you can selectively on/off different kinds of checking in ERC (I read the forum all the time even last year I had a break in PCB designing.

Edit.
I am surprised.
I cited the message to what I am answering. When I posted the cited message dissappeared. I added it once more. All process took only few seconds and it was shown that I edited message twice.

Adding this Edit did not increased the counter.

But adding previous sentence increased

[Sprig]

@craftyjon

The way to fix this is as the ERC says: make sure a net that is connected to a bus is actually a member of that bus.

That was NOT obvious to me. I’ve spent hours trying to learn how to use the KiCad bus system. I’ve now reached a starting point.

The issue is that people like you understand the basics; while I had not a single clue where to even start. Without some hints from this thread, and others, in this forum, I do not think I could figure it out from the official documentation at all.

I’ve got some more tinkering and learning to do. Maybe when I am more comfortable that I really do know what I think I know I may create a simple tutorial.

I am extremely grateful for every who posted in this thread. There is no doubt in my mind that I would still be lost if not for the guidance given here. Thank You!