(SOLVED) Annoying issue with PWR_FLAG. Hierarchical labels seems to be connected globally

[leoheck]

Hi guys,

I have a circuit with a hierarchical design where a sheet is instantiated 3 times.

I had no issues with these PWR_FLAG but after importing circuits from another sheet with the Append Schematic Sheet Content tool, Kicad started to complain about these PWR_FLAG's.

I have no idea what to do to fix it. Do you have any input for me on how to fix this?
I also tried to remove all the PWR_FLAG and add again but it didn’t work either.

The text output is more clear

ERC report (Sat 11 Jul 2020 18:03:40 -03, Encoding UTF8 )

***** Sheet /

***** Sheet /Homebase/

***** Sheet /Coprocessor_1/
ErrType(5): Conflict problem between pins. Severity: error
    @(55.24 mm, 51.43 mm): Pin 1 (Power output) of component #FLG0105 is connected to 
    @(55.24 mm, 51.43 mm): pin 1 (Power output) of component #FLG0107 (net 140).
ErrType(5): Conflict problem between pins. Severity: error
    @(55.24 mm, 51.43 mm): Pin 1 (Power output) of component #FLG0107 is connected to 
    @(55.24 mm, 51.43 mm): pin 1 (Power output) of component #FLG0109 (net 140).

***** Sheet /Coprocessor_2/
ErrType(5): Conflict problem between pins. Severity: error
    @(55.24 mm, 51.43 mm): Pin 1 (Power output) of component #FLG0105 is connected to 
    @(55.24 mm, 51.43 mm): pin 1 (Power output) of component #FLG0107 (net 140).
ErrType(5): Conflict problem between pins. Severity: error
    @(55.24 mm, 51.43 mm): Pin 1 (Power output) of component #FLG0107 is connected to 
    @(55.24 mm, 51.43 mm): pin 1 (Power output) of component #FLG0109 (net 140).

***** Sheet /Coprocessor_3/
ErrType(5): Conflict problem between pins. Severity: error
    @(55.24 mm, 51.43 mm): Pin 1 (Power output) of component #FLG0105 is connected to 
    @(55.24 mm, 51.43 mm): pin 1 (Power output) of component #FLG0107 (net 140).
ErrType(5): Conflict problem between pins. Severity: error
    @(55.24 mm, 51.43 mm): Pin 1 (Power output) of component #FLG0107 is connected to 
    @(55.24 mm, 51.43 mm): pin 1 (Power output) of component #FLG0109 (net 140).

 ** ERC messages: 6  Errors 6  Warnings 0

[leoheck]

It is interesting that this is happening with one PWR_FLAG, but it does not happen with another.

So, it affects, #FLG0105, #FLG0107, #FLG0109
But doesn’t afftect #FLG0104, #FLG0106, #FLG0108

This is the content of the sheet (only the important part)

[iabarry]

You should only have 1 instance of the PWR_Flag for a given voltage. The flag is a voltage OUTPUT and you don’t want to have multiple tied together.

[leoheck]

Yes agree, but I have it.

I have 1 sheet (called microprocessor) that was instantiated 3 times in the main sheet.
So, 3 microprocessors were instantiated.

This microprocessor sheet has 2 circuits that needs power flags. I added them and this was working pretty fine during days.

Now, after importing some circuits from another project (from an external schematic sheet) the ERC started to accuse one issue. AND as you can see there, the ERC reports only PWR_FLAGS which means they are being interconnected which should not happen.

I put one PWR_FLAG for each given voltage.

Now, one of the PWR_FLAG's inside this microprocessor sheet works without any complain. But the second is giving me this ERROR.

[leoheck]

Ok, finally found it. SOLVED!

In this new imported circuit I was using a GLOBAL label with the same NAME as my LOCAL label. Then the wires were connected together.

So, it is not a bug. It was introduced by myself and it was really hard to find since the labels were equal, which is that I want in the first place but I was not able to spot the GLOBAL connector easely.

[iabarry]

If things are tied together, then there must be a common label name.
Look at node names on the individual sheets.
Once they are all in the same project, all +5V will be tied together,
regardless of sheet.