[SOLVED] All GND pins on components connected to 1V0!

Hi,

I am trying to add a 1V0 power port to power my FPGA (Artix 7 35k cells) as shown below:

When I run pcbnew to layout the board and read the generated netlist, for some reason the report says all GND component pins were changed to 1V0.


J2 is supposed to be GND, but is assigned to 1V0

Could someone please help me out.

Thank You

Somewhere you have accidentally connected 1V0 to GND. Without access to the schematic we are no wiser than you are.

Try dragging the components between 1V and Gnd to see if there is a wire underneath

@bobc, @davidsrsb here is my schematic pdf

schematic_latest.pdf (1005.8 KB)

and a zip of the complete project, we are trying to modify the hackrf one to include an fpga.

noob-sdr.7z (2.4 MB)

I did that there is no wire between 1V and GND.

*cough*

By searching for “1.0V”, I found you have +1.0V connected to GND here:

If you have two labels on the same net, KiCad picks one of them semi-randomly. So although the bug was already there, adding a new occurrence of +1.0V exposed it.

You might wonder why having different power labels on the same net doesn’t flag big red warnings, and that is a good point. I think the handling of labels and power symbols could definitely be improved.

Joan ninja’d me :slight_smile:

I would also wonder why VMGTAVCC is connected to GND… I don’t think that is what the datasheet recommends!

And the net highlighting in the nightly builds helps find this sort of error too.

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oops, thank you very much everyone.

I am not really using the GTP, which is why I connected it to ground.

Looks like you owe to @Joan_Sparky, and @bobc, and @John_Pateman a serving of their favorite malt beverage, to ensure that neither your co-workers nor your supervisor learns of this incident from them!

Dale

Yeah, I do owe you guys a malt :grinning:, although I think it might go bad if I have to mail it you from Bangalore. So the next best thing is probably this @davidsrsb, @Joan_Sparky, @bobc, @John_Pateman, @dchisholm

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