I’ve added a number of vias to my PCB. Basically all the vias are marked as an error since the annular ring is too small (based on the default constraints). I can’t for the life of me understand how to solve this issue, by making it so that the annular ring is wider. I’ve tried adding teardrops, or whatever.
Vias have two diameters, hole and (total) via. Annular ring width is via minus hole per two. Make the via diameter larger.
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Is the constraint you have set, even if it is the default, correct for the PCB fabricator you plan to use ?
I’m supposed to use JLCPCB. Their standard via size is 0.3mm for the holes, and they recommend 0.45mm for the diameter. So I should be in the clear, but because that works out at 0.075mm for the distance between hole and ring, KiCad complains as its default is 0.1mm. So I suppose I just have to set the constraint smaller.
Or just use a bigger via pad and keep the constraint, JLCPCB won’t mind a bigger via pad.
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0.3 / 0.45mm via is manufacturable by JLC without extra cost.
So, yes - change KiCAD constraint.
And make sure other constraints are also correct before you start laying tracks.
Check JLC capabilities on their website and manually change constrains in KiCAD or use rules people share on GitHub, for example here:
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