Soldermask missing between pads

My new board (almost) failed. I uploaded my design to the fab house, checked the preview and noticed a solder mask error. The board contains a small TSSOP-8 and the solder mask between the pads was missing.
I checked the Kicad design and it was fine, both in the designer and the 3d viewer. I did not use Gerber files.

With great help from fab house support the problem was found.
The problem was the setting ‘Solder mask min width’. This can be found in: Pcbnew > Menu > Setup > Pads to Mask Clearance. It was set to 0.25 mm (0,009842519685 inches), Kicad installation default.
(This is in Kicad 5. I’m not sure but in Kicad 4 it may be “Minimum mask web clearance” in the “Mask Pads Clearance” menu option).

The problem was solved by changing the setting to 0.1 mm (4 mil) in accordance with the fab house spec.

Regardless of the setting, the Pcbnew designer and -3D viewer always show the same solder mask. Changing the setting does not cause a visible change in Kicad. And therefore it may show a correct solder mask, where in fact it is incorrect.

So two questions.

  1. Is the default setting of 0.25 mm excessive?

  2. More important: shouldn’t Kicad show the correct solder mask?


It has been noted before that default clearances do seem to be a tad generous for a lot of settings. Keeps really stupid people like myself from making gross errors. The low end board houses that hacks like myself use need the larger tolerances though some may simply be hold overs from times when board houses weren’t quite so sophisticated.

The 3D viewer is a great aid and should show correct values most of the time but

This is always considered the final ultimate check as these are generally the files you upload. Did this place use the Kicad files directly?

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In my opinion it is.
Do a Google search for “solder mask defined pads”.

While the board house I’ve been using recommends a clearance, my designs typically come back just fine with the solder mask set to 0 (zero). I had a design fabbed with a KiCad library footprint, 8-MSOP, and the clearance set to zero and the footprint for those boards turned out perfect.

Do be mindful that this is information is presented as my experience with one particular board house; YMMV.

As one point of argument, there is nothing automatically wrong with having no solder mask between pins, sometimes it is needed for very tight pitch components and sometimes it is MFG recommended. It can make hand soldering problematic. For SMT Assembly a solder paste stencil is created that only applies solder to the pad surface.

If you are designing for Solder Mask Defined Pads, then a negative clearance has to be specified to have the mask overlap the pad.

If you are designing for Non Solder Mask Defined Pads, then some positive clearance needs to be specified. \

A clearance of 0 is not a very good solution, because it can cause your NSMD to become SMD and vice versa if the fab takes you are face value, but more often than not they will tweak it depending on their interpretation of that. You should set the clearance to your fab manufacturing house clearance if you have tight pitch NSMD pads.

I suspect that mask pullback setting is applied before plotting and not computed on the fly, which is why it is not showing up except in fab outputs.

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Since I remember we use 3mils in our designs.
And if the distance between pads is so small that solder mask left would be 3 mils (i.e. distance of 9mils) you shold not put solder mask there. Too narrow solder mask can be broken and moved to random position on PCB and disturb soldering.

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Careful which setting you are referring to. There are two here, mask clearance and minimum mask width.

Solder Mask Defined Pads is generally done with the clearance setting by setting the spacing of the mask edge positive or negative relative to the edge of the pad.

The issue the OP was wrestling with is the minimum mask width setting which defines how thin a single web (line) of mask can be between two mask openings. Usually this is the mask webbing between SMT pads. Some mask processes can cause issues where if the web is too thin then the process of removing the mask material where the mask isn’t needed can flake these really thin webs up, potentially depositing the floating web in the middle of a pad right before the final curing.


I followed @hermit 's lead; however, I don’t think hermit was wrong. I just tested the OP’s settings on a KiCad library footprint and changing just the width to 0.1mm did not fix the soldermask. Changing the clearance setting, and not the width setting, allowed for proper solder mask between the pads.

I still recommend that one does a Google for the difference between soldermask and non-soldermask defined pads.

Also, there is a good discussion somewhere on this forum, about the expected results when the minimum soldermask width is set to a value that is slightly under the fab house recommendations.

Preferences/Display Options ensure that “show solder mask layers” is checked; and maybe also “realistic mode”.

Thanks a lot for so much information. I’m learning a lot here.

It’s true however that I’m wrestling with the minimum mask width setting.
I did some googling and have yet to find a value over 4 mil.
Also I tried a few open source designs with a TSSOP-8 that are supposed to come with solder masks between the pads (for hand soldering) and they would fail using the Kicad default setting of 0.25mm (about 10 mil).

Therefore for me the Kicad default of 0.25mm for the minimum mask width setting would be an unsafe large default. (Of course I’m just one world of many…)

They are both checked.

Since we are talking about Kicad settings, I still believe Kicad should show the correct solder mask and update it if the minimum mask width is changed.

Should I report this as a bug?

I think you meant under.
What board fab house did you send your files to, and what is their recommended minimum mask width?

FIrst, ensure for certain that you understand what you are looking at. The soldermask layer in PcbNew shows where soldermask will not be applied; it is an inverted layer. When the 3D viewer is used, the image should show the soldermask with varying “holes” in it.

At this point, a screen shot of your perceived issue would really help clarify the problem that you are actually having.

What is shown on the mask layer in PCBNew as @Sprig pointed out is the inverted layer of soldermask (where it isn’t).

I verified on Kicad 5.0.1 that the mask layer does not automatically add graphics to cover the places that would be excluded due to minimum mask width which I believe is what you are asking for. Without this, it the final mask layer is not shown in any preview (2D or 3D) and is only visible in the gerber plots.

The picture in your head may be something like a polygon pour, where the soldermask would reflect the minimum width and spacing with every update. Unfortunately, this is not the case, while pads are updated in real time with the clearance value, the minimum spacing rule is not applied in the preview.


No, I definitely mean over.
The values I have found so far for the minimum mask width are: 2 mil, 3 mil, 4 mil and 0.1 mm.
4 mil / 0.1 mm seem to be the most common, I have found these at Oshpark, SeeedStudio, Pcbway, Adafruit and it’s the Eagle default.

@crasic Thank you very much for confirming my observation.
And yes, you are spot on. A graphical piece of information representing the minimum mask width was exactly what I was expecting.

Which leaves me with one confusing point.
The minimum mask width is presented as a Kicad setting. Similar to it’s neighbor Solder mask clearance (Kicad 5!). Which is why I expected it to show up in the designer or viewer in the first place.
However it’s seems more commonly being treated as a fab house dependent DRC value. In which case I would expect a DRC error or warning.
Neither happens.

So if this is not a bug and by design, I would very much like to learn the rationale behind this.

Minimum mask width isn’t used in DRC. When gerbers are created the mask layer is modified so that it doesn’t have thinner mask strips than this value.


It does not seem that you looked very hard; my second page:

When specifying a mask color other than green, the min width is 150µM (which is about 6 mils).

Fab houses are going to have difficulty going smaller, not larger. It was not that long ago that OSHPark was specifying 6 mils minimum.

Solder Mask Clearance

For almost all boards, a mask expansion of 0 works perfectly fine.

The 3D viewer is not meant to be the final check of the board design; the Gerber files are.

Set the Pads to Mask clearance to zero, the width to 0.004", and the boards you recieve from OSHPark will look exactly like the 3D viewer (assuming of course that you change the soldermask color to purple!).

100µm = 0.1 mm = about 4 mils, not 6. Tonn said it’s the most common value and couldn’t find values over it. 6 would be over 4, but 100µm is 4 mils. However, for color other than green PCBWay has the minimum value of 150µm which is about 6 mils, is that what you meant?

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Arggh, I hate making misteaks like that!

Thanks for the catch!

Ah, thanks!


I think I now have more than sufficient information to adjust my expectations and assumptions.
Everyone, thanks a lot for your help.


The gerber files are used as a check tool as these are typically the files you send to your manufacturer. If you send them the kicad files directly then you need to hope that they use the same export settings as you did when you made your checks. (This is why i personally would never ever send anything else than gerber.) You also need to hope that they have the same version of KiCad as you do.

Additionally: if you set the mask clearance to 0 you will not get the board back as shown in the gerbers. The board house will adjust the clearance to their value. (a good board house will ask you what to do -> Will take time but at least you get feedback.)
In such a case it could happen that the gerber looks like you have enough space for solder mask between two features. After increasing the clearance to fit the manufacturing requirements the minimum width settings might already be violated. (Resulting in no solder mask between these features)

I personally would not go down that route. I always carefully read the manufacturers documentation and setup kicad to fit their restrictions. (In most cases i don’t go to the limit if i can avoid it.)

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This statement is absolutely incorrect when using OSHPark as the fab house.

From design specs side of oshpark:

Maximum soldermask expansion, retraction, or shift is 3mil (0.0762mm).

This means they only guarantee your pad to be non solder mask defined if you leave a clearance of 3mil. I therefore see two options of what will happen if you send a board with 0 clearance:

  • Option 1: They add their clearance without ever telling you. (Might be the reason why you state that it “works”)
  • Option 2: They manufacture it as given. Some pads might be covered with solder mask. See below for more details (It might not affect your manufacturing process. This might be why you would state it “works” in your case.)

Analysing option 2:

Lets simplify the oshpark definition and assume all the error comes from a misalignment of 3mil between copper and mask.
For further simplification lets assume the alignment issue means the soldermask is moved to the right by the full 3 mil.

So if you had your soldermask beginning exactly at the left edge of a pad then you will get it with 3 mil covered on the left side and 3 mil free on the right. (In reality this will be a bit different as you will never have alignment alone nor exactly in one of the orthogonal directions.)

For handsoldering this is probably ok. This is because you normally already have much larger pads than strictly necessary. For reflow soldering one might not be able to live with such a discrepancy. (Especially not in high volume production where you want tight control over all of your parameters to increase yield and therefore your profit margin.)

My definition of “getting something as designed” would mean that the obove listed option 1 is definetly wrong. Option 2 can be considered within specs if i assumed this to be the case during footprint design. Otherwise it is definetly the fault of the guy setting up the design tool parameters. (The board house did what they where told.)

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