I use the library footprint “SolderJumper_2_Bridged” in my PCB which causes a DRC violation.
In schematics, the bridge jumper is coming from the PWM pin (which is also VREF) and is connected to 3.3V. When I connect this in PCBnew accordingly, it will lead to a clearance violation.
It is a two layer board. Top layer is 3.3V and the bottom layer is GND. Therefore, the BR1 pad is connected to the top layer with one pad.
I have tried to change the minimum clearances in the properties on the pad in PCBnew but this didn’t helped.
Is there a possibility to get rid of the DRC other than set this error to ignore?
Or should I just ignore the error? I think, technically it isn’t a fault.
I just ran into the same problem. Net ties (which this is from a technical viewpoint) have been problematic and the implementation has been changed. My opinion is that this is a bug. A polygon or other copper item which shorts two or more pads in a footprint which has shorting net groups defined should be ignored for the corresponding nets while routing and in DRC.
Thank you two for the confirmation. I wasn’t 100% sure if I should just ignore it. But have now a better feeling that I don’t order a malfunctioning board soon :-). Thanks.
For me, Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm does not generate any DRC issues.
However, if I edit the Footprint properties and delete the 1,2 Net Tie in the Clearance Overrides and Settings, then I do get the copper polygon violation.
