Hello
I ordered some PCBs from JLC along with a stencil. I populated the board manually after applying T4 paste with the stencil and reflowed in a small oven. The stencil has a thickness of 0.12 mm.
I set -5% solder paste relative clearance in board setup but the results were not that great. I had to rework a lot of bridges on an LQFP-48 part with .5 mm pitch. The remainder of the board are parts with a far coarser pitch (SOT-223, SOIC-16W, 0805) and those reflowed flawlessly. The rework was easy to do but I am convinced that I can improve my process.
Do you recommend reducing the relative paste clearance further? To what number? Is the percentage I enter in “board setup” relative to the area/volume or to the length of the edges of the pad? Also, I tried to set it to -50% to answer that and then the paste aperture completely vanishes, which has me confused.
I am happy for any advice. Thank you and best regards!
Matt
KiCad Version Info:
Application: KiCad PCB Editor x86_64 on x86_64
Version: 9.0.4-1.fc42, release build
Libraries:
wxWidgets 3.2.8
FreeType 2.13.3
HarfBuzz 10.4.0
FontConfig 2.16.0
libcurl/8.11.1 OpenSSL/3.2.4 zlib/1.3.1.zlib-ng brotli/1.1.0 libidn2/2.3.8 libpsl/0.21.5 libssh/0.11.2/openssl/zlib nghttp2/1.64.0 OpenLDAP/2.6.10
Platform: Fedora Linux 42 (Workstation Edition), 64 bit, Little endian, wxGTK, X11, gnome, wayland
OpenGL: Intel, Mesa Intel(R) Iris(R) Xe Graphics (RPL-U), 4.6 (Compatibility Profile) Mesa 25.1.7
Build Info:
Date: Aug 18 2025 00:00:00
wxWidgets: 3.2.8 (wchar_t,wx containers) GTK+ 3.24
Boost: 1.83.0
OCC: 7.8.1
Curl: 8.11.1
ngspice: 44.2
Compiler: GCC 15.2.1 with C++ ABI 1020
KICAD_IPC_API=ON
Locale:
Lang: en_US
Enc: UTF-8
Num: 1’234.5
Encoded кΩ丈: D0BACEA9E4B888 (sys), D0BACEA9E4B888 (utf8)