I’m using a library footprint (Package_DFN_QFN:UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm). The Exposed Pad’s and all the signal pads’ (Top) Solder Masks are merged due to some expansion I don’t understand. When I look at the board in KiCAD (PcbNew), I see a reasonable mask - a bit larger than the copper as expected. [Solder mask clearance is set to 0.05 mm.] This is a portion of the PcbNew screen:
However, all external tools see the (open) mask area merged due to what seems like excessive expansion. This is the same area as shown by an online viewer (Gerber-Viewer.com) but OSHPark and the built-in gerbview show the same outline:
I must be missing some setting or concept (or likely both). This isn’t my first KiCAD project but I’m far from an expert. Any suggestions would be appreciated.
Min width does not “expand” your soldermask (this is what soldermask clearance does). If the minimum width is violated then the two mask sections that are too close to each other are connected. (Min width is a manufacturing constrained. If it is violated then you can get delaminated and broken mask layers. That broken piece can lodge itself between a pad and lead resulting in problems with soldering. Gerber export removes the mask in such cases to avoid this problem.)
To avoid kicad connecting two nearby mask sections you will need to reduce min with and/or reduce mask clearance. There are however limits on how far you can go with these (see your manufacturers capabilities)
So if you go to the absolute limits of what your fab can handle with these settings but kicad still connects them then either switch fab or select a component that has more clearance between pads. Or accept that there is no mask. Generally reflow soldering should still work without mask assuming you have your paste application under control.
You are absolutely correct. I misinterpreted the views. I apologize.
I tested 0.00, 0.05 and 0.10 mm minimum widths and the mask did not change size at all when viewed with gerbview. I will use only gerbview in the future.
I understand, after a fashion at least, the issues for manufacturing.
Unfortunately, this component (PIC16F15344) does not come in a 0.65mm pitch leadless package which I’m comfortable with. And that seems to be the trend. More and more I find only 0.5mm pitch components. I may have to use the leaded package but it takes up much more area. I’ll check with my fab to see if they can live with 0.10 mm minimum width (alternatively the 0.5mm pitch package which is almost the same in this case).
I would have been less ignorant had I read your FAQ first. But I don’t guarantee I would have understood my issue. Thanks to both you and Rene for pushing me in the right directions.
Can you say how it could be better? I wrote it quickly after two similar problems in two threads, so it’s not perfect. Maybe it needs full rewrite later, but I can edit it now if I get some feedback.
I’ve got into the problem of not enough place for solder mask between pins few years ago, but it was 0.4mm pitch.
With 0.5mm I think there should be no problems. My setting (since more than 20 yaears) is 3mils pad expansion when solder mask generating. Till that 0.4mm pitch problem I have never heard about minimum solder mask width, and at that occasion I was told that that minimum it typically also 3 mils.
If you have a problems with 0.5mm pitch I think you can:
made pads a little bit thinner,
made thermal pad being not copper defined but solder mask defined (solder mask opening smaller that pad).
Good advice, especially about the thermal pad. I almost always do as you suggest, but in this case I just used the official library footprint supplied for the package. I will go and “personalize” it and see if I can get a minimum width of more than 0.10 mm. I did test and 0.11 mm is too large in the sense that the EP merges with the signal pins when using the official library footprint.
For the record, my Solder Mask Clearance is 0.05mm or about 2 mils.
For now, I’m going to try to keep the pad width the same as the official library as it seems to correspond to most chip makers’ recommendations. But if I have issues, I’ll do that next.
Finally, I have to gather these issues and talk to the fab shops we use, including OSHPark and the two local vendors we use.
I’ll review that FAQ soon but the main issue I had was I didn’t find it before starting this thread. Nor did I see the two threads that covered essentially the same issue. Sometimes it’s a matter of the search terms - I’m not all that good at picking them. I DO always search first, but with limited success it seems.
Going to soldermask defined does not magically increase the clearance you have available. (you would then run into the problem of having the copper pad to pad clearance reduced as you will still need to fulfill the mask to coper clearance but this time in the negative direction. And you can not really decrease the area required for the EP as you would then run into problems with reduced self alignment -> makes reflow soldering much more unreliable.)
So the better option might be to decrease the heel fillet for the outer pads in preference of modifying the already small EP (EPs are created equal to the nominal size of the package pad. This is equal to quite a bit negative fillet size.)
With you using OSHPark I recommend setting the Solder Mask Clearance to Zero(0.0), and the minimum also to Zero(0.0).
This has been an ongoing issue for me to understand for a couple of years now. In that time I have had discussion on this form and received OSHPark boards with the clearance setting I recommended above.
Now, the minimum width is interesting. Parts are getting smaller and smaller, why would you want to NOT attempt to put SolderMask between pads of Stupid Small Parts? In both Hand-Solder and Reflow-Solder any minor SolderMask should help to reduce solder-bridging.
Also take note that the 5.1.X nightly that I am using seems to have defaulted to zero and zero for these settings; I am not using Templates yet.
Also note that I have watched University of YouTube videos as well as going On-Site to a highly rated board assembly house and talked with some of the lead… Well, I still set the clearance to Zero(0.0).
As has been mentioned before, the limit for mask width between openings in the mask is a manufacturing limitation. Depending on the specific process (and/or materials) that the manufacturer uses they tell us, the designers, the minimum width that works to reliably reduce the problem of really thin bit of mask detaching from the board and then being deposited on pads. If we, as designers, really desire thin dams of mask between pins of “Stupid Small Parts” (I like your phrase) than it is up to us to shop around for a manufacturer that can meet our design requirements.
Lets assume they then really produce with both set to 0 (Meaning they do not change the specification you sent)
This would be the worst option for manufacturing as any alignment issue between soldermask and copper guarantees that the useful area (exposed copper area) of your pads is reduced. It also guarantees that a lot of soldermask edges are very near to steps in copper which increases the risk of delamination.
So you see the clearance specified by manufacturers is there for a reason. (And it applies to both soldermask defined and non soldermask defined pads. There simply is an area where the manufacturer is allowed to tell you that it represents undefined behavior. Comparable in this regard to a digital signal pin that has a voltage range where it has undefined behavior.)
The manufactuer has two (and a half) options. Produce as specified and assume you are aware of reduced pad areas which will result in reduced yield in both a well controlled reflow process (you introduce another variable to the mix) and with regards to soldermask adhesion. If you carefully crafted your footprints in accordance with IPC guidelines you now no longer have a product that fulfills these. After all the paste cutout is designed with the assumption of having the full pad size and you therefore have too much solderpaste.
The alternative is that the manufacturer could (possibly without telling you) generate the soldermask using their tools if they discover what you sent violates their constrains. This will mean that you will discover the problem of connected mask areas when holding your boards in the hand instead of when generating the gerbers (a bit late to do anything about it). It also means that the final product is always in violation of its specification (gerbers are manufacturing specifications).
Conclusion: If you do not care about specification violations then you can live with option 2 of the manufacturer. If you do not have a highly optimized assembly process then you can even live with option 1 (If you hand apply solderpaste. Especially if you do it without stencil.)
Those manufacturers who ask you to use zero set the proper values themselves, they adjust the mask layer to fit their processes. They don’t use zero even when you do. Probably most manufacturers do that adjustement if they see you have used zero.
… (EPs are created equal to the nominal size of the package pad. This is equal to quite a bit negative fillet size.)
Rene:
Regarding the bolded (by me) part of your post:
The 5.1.4_1 (Windoz) installed library’s footprint (Package_DFN_QFN:UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm) EP measures 2.8 mm x 2.8 mm as one would expect. The EP of the device (Microchip PIC16F15344GZ) is 2.6 / 2.7 / 2.8 mm. min / nominal / max - both width and “height”. See http://ww1.microchip.com/downloads/en/DeviceDoc/PIC16-L-F15324-44-data-sheet-40001889B.pdf, page 551 and 552.
It seems to me that for this part at least, the library EP is not the nominal size of the EP but the maximum size. The library’s EP dimensions are exactly what Microchip recommends (2.8 x 2.8) for the EP’s copper. But it seems to be the maximum EP size, not the nominal.
It may be that 2.8 mm is the nominal size of the EP for parts from other vendors. But I checked quite a few of Microchip’s “GZ” parts and they all specify the 2.6 / 2.7 / 2.8 mm dimension for the EP.
[Note also that the '15344 is not in the KiCAD library so I used another Microchip part that uses the same package and pinout and re-labeled it.]
This is in no way a criticism of the libraries. I’d sound like a schoolgirl with a crush on you and the rest of the team if I tried to express my appreciation for the effort made in organizing and creating the libraries.
I’d just like clarity on the best practice.
Note I will follow your suggestion to reduce the heel fillet first unless you feel for this part it would be better to make the EP’s copper the nominal size as specified by Microchip (2.7 mm). My prediction is that you will say keep the EP at 2.8mm and get the extra space (if needed after consulting fab) from reducing the heel fillet.
We allow contributions to deviate from EP is nominal as long as the datasheet suggests it that way AND it is within minimum and maximum size (If larger than max a soldermask defined pad must be used.)
