I had to populate a board yesterday and I was surprised to see that I could not see the polarity marker of a diode and I had to go to Pcbnew to check, at first I thought I had make a mistake using too big clearances for my signals but they were set to 0,2mm, I even changed them to 0,15mm and after clicking on the component on the board for the settings to take effect the Gerber files were showing the same problem.
It has the silk line at -1.5, pad at 1.05 with size 0.6 -> left side of pad is at -1.35 -> silk to pad clearance is then 1.5-1.35-0.12/2 = 0.09 which is indeed a bit small.
Meaning yes this footprint could really benefit from an overhaul (preferably with the scripts). Created an issue about that: https://github.com/KiCad/kicad-footprints/issues/1425
Additionally: The copper clearances are not what defines the size of soldermask. This is a separate setting in the paste and mask clearance dialog.
Sadly i can not remember from the top of my head where it is found in 5.0.x Neither how exactly it is called in that version. My guess would be in the setup menu. (In current nightly it is under file->board setup but that does not exist in that manner in 5.0.x)
Some PCB manufacturers will print silkscreen where your gerbers tell them to even if across copper. (Don’t ask me how I know this…) Others will automatically mask the silkscreen with either the exposed copper or the solder mask (different ones will do different things).The better ones will flag the potential issue and verify with you what your design intent was.
That said, in KiCad gerber generation there is a flag (I think it defaults to ON) to mask the silkscreen with the solder mask, essentially cutting away from the silkscreen every place where solder mask won’t be applied.
Maybe a feature request for the 3D viewer should be a toggle to mask or not mask the silkscreen with the solder mask… (To replicate the function of the flag in gerber generation.)
Neither KiCad nor the PCB manufacturer can now what the designer wants to happen in such a case.
Getting the soldermask substracted from the silkscreen is common, but if the board manufacturer does not do it, then you risk silkscreen text over pads.
A very nice solution would be to add an extra option to the DRC checker.
It already has a separate button for for listing unconnected pins.
What do you think of a 3rd button with “beauty rules”
It could check for silkscreen that is not on solder mask.
It could check for overlapping texts.
It could check for text / silk screen art outside of the PCB Edge.Cuts.
It could check for text that looks mirrored after PCB manufacture.
It could check for other things that are not really errors, but might want attention.
I do not agree here. This leads to production delays which can be far more irritating / costly than the issue itself. I once missed an E-mail from Mouser. They told me I had to sign a form to promise I was not a terrorist. I missed that mail, which caused a month of delay before I started looking into what happened. It resulted in me cancelling the whole order, and buying my Beaglebones in Germany.
The “Beauty Rule Checker” would leave the initiative to the designer, and even rookies in PCB design will probably find the button and start thinking what the board would look like in cases such as the reason for starting this thread. Things like Silk screen getting erased by expanded solder mask clearance is easy to miss on a board.
At the moment the DRC does not seem to check at all for silk screen text outside of the Edge.Cuts. In another PCB program this was handled just like any other DRC error, which was annoying while routing a board. I wanted to get the routing done before spending time on secundary things such as silk screen text.
Which is why I said that the better manufacturers will flag this and ask what the designer wants.
I can imagine artistic reasons to allow silkscreen over pads. (Not electrical reasons.) I have had in the past a manufacturer print silkscreen on my pads because in my naivety I expected them to do the masking of the silkscreen with the solder mask for me. They didn’t, and didn’t double check with me. I was left scraping silkscreen off of pads to get good solderability.
That said, in KiCad the designer has the option to do this at gerber generation time. And has from at least before v4. Your DRC addition options might be useful addition to KiCad. Maybe an additional one that flags only text that isn’t over solder mask (or 3 options in your furst suggestion using a drop-down; all, lines/graphics only, text only). That way if one doesn’t care about lines getting masked one can focus only on making sure ref’ds don’t get obscured accidentally.
I do not agree with this. If small things get flagged and questions get asked, then this causes unneeded delays, which can be costly. Time is often important.
That is a good lesson. You will not make that mistake again. KiCad has plenty of ways to prevent it, starting with putting texts on proper location (Silkscreen Text unreadable because of via holes is also common).
Things like this also clearly stand out in the 3D viewer. At first I thought the 3D viewer more of a gimmick than a usefull feature, but it really helps in spotting errors beause the usual PCB view is cluttered with lots of things.
Reviewing one layer at a time, or combinations of a few layers also help as a final review before manufacturing a board.
There are valid arguments on both sides of the question. Losing a day due to back-and-forth between the designer and board fabricator is the price you pay for ensuring that the board you receive, is the board you had in mind when you ordered. Receiving boards that must be manually reworked (scraping silkscreen off pads, cutting away copper bridges, etc) can cost almost as much in time. Receiving a board with defects, and not discovering the defect until AFTER assembly, AFTER you spend hours (or days) troubleshooting a unit that doesn’t work correctly will eat much more time than having the board vendor say, “Hey, this doesn’t look right. Did you intend to do this?”.
My personal preference is to have the board vendor ask about anything suspicious.
I disagree that KiCAD has “plenty of ways to prevent it”. The most effective preventative measure I know is a realistic and accurate algorithm for detecting silkscreen violations at DRC time. I have used programs where the silkscreen check was unrealistically cautious, and flagged half the silkscreen on the board. You had to either over-ride all the squawks, or turn “OFF” the silkscreen DRC altogether. (Either of these violates the whole purpose of the DRC.)
Like you, I always take time to do a thorough final review (preferably, a day after I actually worked on the board) looking at specific pairs of Gerber files, selected to emphasize particular types of errors.
