SMD standoff footprint errors

[AdriZ]

I hereby certify that I am not simply asking someone else to design a footprint for me.

Hi,
I used the footprint Mounting_Wuerth_WA-SMSI-M3_H13mm_9774130360 from the official library.
It corresponds to this component: 9774130360R.pdf (we-online.com) which is a SMD standoff.

I got the follwing errors.

I saw the footprint has 3 strange pads:

I removed them, but I still have some errors.
In the footprint editor:

In PCB editor:

I tried a lot of different things, using NPTH or Through-hole without copper (the datasheet recommend Non plated through hole), I had different errors but I can’t avoid them.

Here are the footprint:
Mounting_Wuerth_WA-SMSI-M3_H13mm_9774130360.zip (2.3 KB)
and a test project (including the footprint):
Test2_smd_standoff_footprint_issue.zip (9.4 KB)

Thanks in advance for your help.

[paulvdh]

This footprint is a bit of a weird one.
I pulled some of the items of the library footprint a bit apart to see what it is made from.

1. The Cyan circle is an NPTH,
2. 4 quarter round aperture pads for the solder mask.
3. Circle on F.Fab.
4. Three small pads and one big pad, all with pad number 1.

Multiple pads with the same pad number is normal in KiCad. KiCad has a small problem with the NPTH hole hole. Because of the NPTH, the center (attachment point) of the big donut pad 1 can not be reached, and therefore a few smaller pads with the same pad number have been added. Deleting them is not a good idea.

You have two DRC violations left.
In the DRC window, you can click on the items (not the bold line, but the thin text listing the items) to see in between which parts KiCad found the DRC violation. The **Clearance Violation is between the NPTH and the pads. It is very likely: PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to hole clearance. You can either change this clearance, modify the footprint, or simply ignore or disable the DRC violation.

For the other: Error: Front solder mask aperture bridges items with different nets I am not sure whether this is a bug in KiCad, or just a bit over zealous DRC. The NPTH must be (and is) covered by the solder stencil, or else the whole hole would be filled with paste during soldering and that would be a mess. It is probably best to disable this error in the DRC window, you can do this by right clicking on it and then click on Exclude this violation in the context menu.

[AdriZ]

Thanks a lot for your reply @paulvdh.

For the clearance violation, the PCB Editor constraints modification works, but I would prefer to modify the footprint, how I can do it? I don’t see where the 0.2mm come from.

[scandey]

If you have any interest in recreating the footprint in a more coherent way, a while back I did a little mini walkthrough on this style of “donut” pad (normally with vias) around a NPTH. Possibly useful here. You’ll still need to be aware of the copper to hole minimum distance though (this is normally set by the manufacturer to prevent later drills in the process kicking up tiny bits of copper by accident).

Inquiry on Designing a Specialized Footprint

If I’m understanding you correctly, the answer is no. There is no concept in KiCad of “anti-pads” as they are sometime described in PADS Layout (an alternative commercial eCAD software). You also cannot make fillable zones in KiCad’s footprint editor, so you can’t make a circular copper pour with a circular keepout zone in the middle to do the same thing.

[AdriZ]

Thanks a lot @scandey, I’ll have a look at that.