Slightly New Label Behavior in 5.1.4 (vis 4.0.7)

…So I upgraded from 4.0.7 to 5.1.4 today. I had the “normal” issues and worked those out.
I cracked open a project that I needed to revise:
I found one problem that I couldn’t easily deal with (that hadn’t been an issue in 4.0.7): I had been (admittedly, lazily) using Hierarchical Labels to connect things within schematics - I’ve actually been doing that typically in many schematics.
In this circumstance, I had two Hierarchical Labels (eventually) feeding into the same pin of an IC: No matter what I did to monkey with the Eeschema file, I couldn’t get one of them to connect to anything, while the other would connect to everything just up to the problem label. I tried quite a few different things and updated the netlist many times in attempt to get the problem label to connect.

I eventually revised the netlabel of the pin object associated with that label (in PBCNew) which kludgily worked, but out of curiosity, I went back to Eeschema and replaced those Hierarchical Labels with ‘Local Labels’ (Net Label) and it totally worked, immediately, with no issues when I updated the netlist of the pre-5.1.4-edited version of the PBC file. ERC also doesn’t like it when you use Hierarchical Labels when all you really need is a Local Label.

The only thing I can glean from this is that there’s been some change to the behavior of Labels between 4.0.7 & 5.1.4; It makes sense, & I knew that I was abusing the Hierarchical Label symbol when using them to connect things on opposite ends of a single page schematic, rather than as an actual Hierarchical Label.

FWIW: Most of the reason I’m using labels at all is that I use single page schematics to create ‘stacking’ PCB projects, so for instance, typically, those Labels feed a pin header (or two) so that I can separate PCBs between ‘front’ and ‘back’ boards. In all case, the ‘front’ is controls (buttons, pots, etc) and the ‘back’ is the brains (power, ICs, etc): I find it much more easy to see both the schematic and PCB on the same page as I negotiate which (mostly passive) element fits best on which board. I’ve been working in this way for quite a few years, but I’m very receptive to suggestion on it - It’s been all really self-taught & what the PCB fabs would let me get away with…

Anyway, I bring this up in the hope that someone having a similar issue in the future will find this post and be able to quickly get their project back on track.

Cheers,
dugan

Not sure what you expect as the result here. Such a connection should connect everything that is connected to both of these labels but only one of these gets to decide the netname (the highlight net tool should show both of them as connected to each other but you will only find one of the two label names in pcb new) If such a connection does not connect everything then there is a bug! (A screenshot would clarify it a bit. But the full project file might be needed to be sure)

More detail regarding net names. If two different labels connect to each other one of their names is taken for the net. Different label types have different priorities which means the chosen name is well specified if two different label types are connected to each other.
However, if one connects labels of the same priority then the resulting netname is unspecified (can change at random -> bad when using anything in pcb new that relies on the exact netname like a zone)

Why hierarchical labels instead of global labels? I can’t understand why you used hierarchical labels in a single sheet circuit. Anyway, I have just tested that hierarchical labels also work in a single sheet circuit in v5.1.4

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