Here is the situation:
-
two classes POWER (big traces and vias) and Default.
-
two nets GND_POWER and GND
I just want a single plane on GND layer with big and small vias according to net classes.
How is it done?
Unfortunately this is not possible. If you want a single connected copper plane for GND, you must have them all on the same net. If you need to maintain separate nets, you need to split the planes and use net ties to connect them together at specific locations.
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That is a very bad situation.
I want currents to find their own way in the gnd plane.
A solution could be changing widths and vias manually,
but errors would proliferate.
I tried putting zero space between split planes but kicad makes clearance room automatically and if I zero it there is no clearance in other places obviously.
What kind of feature request could be asked? any ideas?
My recommendation is to use the larger via size everywhere you can, and then manually make exceptions for small vias where the large ones do not fit.
Isn’t the “size” of a via meaningless in a ground plane?
The via annular ring will be merged into the plane, meaning that only the drill size is different. Just use the largest via you need, and manually change ones that don’t need to be so large to smaller ones. It never hurts to use a slightly larger PTH.
If you wanted to shape this into a feature request: it would probably be something that we consider putting into the custom rule language, and the key would be adding some condition query that selects for vias that are directly connected (i.e. via tracks on the same layer) to pins on certain components.
This would allow you to write custom rules that say “for vias directly connected to device U1, use a larger/smaller size”.
This would only work if you started routing from the component pin, though. I’m not sure it’s an ideal feature to add.
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If I have to do it manually I prefer big holes for big tracks and small holes for smaller tracks.
In the current project I can manage with split planes, but next one I’ll do it manually for power tracks and vias (usually there are less of them).
This has to be corrected, I’ll post a feature request.
A simple option to allow overlapping zones would be nice.
Something like a negative priority maybe?
It’s very simple (if I understand your question correctly).
You can Create a Zone or Track from a Polygon and can use it for the Plane and make settings as needed for viewing…
I didn’t bother to mess with the 3D-Viewer settings but, you can tweak as needed. Also, I reset the Zone fill using the Tools shown in screenshot… I did not resize Vias/Holes but you can do that as needed…
DRAFT-FILL USAGE…
Why not via stitching ?
another workaround could be routing the “two” nets individually and once everything is done, connect them in the schematic and redraw the zones in the layout. you only would need to remember this in the final stages of your design.
May be you could connect them with a dummy part at first. So that you have a drc error (like missing footprint or something), just to remind you that you must do the final “merge” of the 2 nets
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The problem is that the two netclasses would become one and the risk is you forget something set in regard of the use the netclass value and it messes the whole layout up…
Speaking of dummy parts someone suggested a nettie footprint with one smd pad overlapped to a th pad so you “convert” each connection of the big traces to the small default plane. A sort of “ground netclass conveter”.
I am goong to try that, it costs a little schematic-side and maybe some space or overlapping drc messages on the layout side.
Are the large ones all in the same region or all the small one in the same region? Or is there are a other easy way to determine their size requirements based on placement location?
If so you can place a area and add a custom rule for it, like this:
(version 1)
(rule "powerViaSize"
(condition "A.insideArea('powerArea') && A.Type=='Via'")
(constraint hole_size (min 0.5mm))
)
Tested this on a not up to date KiCad 7.99. No idea if it works on KiCad 7.0
Overall they are different regions, but some could be in the same (e.g. a gate driver of a power mosfet kept in the power region).
I haven’t looked at rules yet, but the real problem is using netclasses that are perfect for everything BUT this only-one-big-ground-plane thing.
For this kind of topics, it is very helpful to know how to use custom rules. Read about them and try some of them before you continue with this problem.
Read about them here:
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I’ll study it as soon as possible.
For now the via-like net-tie seems to work:
- place a single zone in the gnd layer called GND
- make a net-tie with a circular smd pad (1) and a through-hole pad (2) with the same center position.
- use the same size and hole diameter of the net-class vias
- in the schematic: put the net-tie wherever a power signal goes to GND_POWER (linked to 1) and link it to GND (2). In this way all grounds go to GND (the power grounds via the net-tie)
- in the layout: place the net-ties as if they are “ready-made” vias
- if you have a th footprint connected directly to POWER_GND (like a source of power mosfet) you have to manually reduce to 0.0001 the pad clearance (should be different from 0) and overlap the net-tie ready-made via with the footprint pad.
- exclude DRCs as needed
Seems to work just fine, I’m going to complete the board and check the gerbers.
EDIT : there is a problem with point 6, if you update footprints from the library the clearance gets reset to its default. Duh.
EDIT2: Silly me, in that case I can connect directly to GND.
Just a little conclusion on the whole thing: I reverted back to single GND signal and routed some enlarged fat traces that I needed to also be on external layers for high current reasons, with a big via near the power connector.
Netclass approach is good for all the other uses, but the ground plane should be treated manually with version 7.0.6
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