The SLC have a top electrode, connected to the bond wires. The bottom electrode is connected to the ground plane. In the current setup I am going to use no cavity but place the chip and SLCs directly on the top layer of the PCB. In my old EDA program I just introduced a new copper layer above the top layer to realize the pads of the Chip and top electode of the SLC and drew thin traces to represent the bond wires.
This has some drawbacks and since I am new to KiCad I would like to get some suggestions how to manage this type layout in a convenient way.
thank you for your reply. I do the chip glueing/bonding manually by my own. So I do not need any exported data from kicad - just the gerber files for the PCB manufacturing. However - I would like to draw the single layer capacitors (SLC) in the schematic as a capacitor and the bond pads on the chip as pins on the schematic symbol.
My problem is how to draw a appropiate layout footprint since there is no layer F.Bond or similar where I can draw the pads on the top side of the SLC nor the pads on the chip.
The ugly way around would be a big layout footprint that contains the bond pads on the top copper as well as some bottom connections for the SLC and the copper to glue the chip on. But this would result in a new footprint for every SLC/chip combination and the schematic would not represent the connection between SLC and chip (and maybe other wirebonded components like resistors).
So I would like to draw each wirebondable component separately in the schematic and the footprint editor and connect them in the layout only. Do you have any idea if this is feasible?
KiCad only allows pads on Front,Back or all layers, so that means you can’t nominate a copper layer for the “virtual” pads. You could use one of the technical layers, e.g. Eco1, but you can’t route tracks on that layer, you would have to draw polylines. That might be sufficient?
