Simulating DDR3 after routing?


Dear Members,

Is there anyway to simulate my routing for DDR3, before I put it on manufacturing ?
What’s the software ?

Thanks for the info,


You would be looking for a 2.5D or 3D feild solver simulation package, they are not cheap.

If you follow the best practices for DDR3 published by a number of manufacturers, you should get close. e.g. length matching, sizing traces for impedance, etc. and decoupling, high speed stuff always needs good decoupling.


The Olimexino64 uses DDR3 and you can find it as a KiCad project on github and on the “made with KiCad” page.
You might want to look it up for the design choices Olimex made and compare it to your own design.


Thanks guys for the info,
I use a chip from samsung, will it be the same or nearly the same with micron ?
Or you guys have info / application note for samsung chip ?



It’s 4Gbit Samsung chip

Anyone ?


This looks like basic comparison of datasheets with KiCad’s footprints etc.
Not a question anybody who is not intimately familiar with both those chips could easily answer.
And there are probably tens of thousands or memory chips made and they become obsoletel weekly or so.

My best guess is you should do you own homework here.


Hehehehe, ok, it’s my homework…thanks

  1. Calculate the impedance of the tracks you are using. As long as you didn’t use (too many) via, a simple calculation is enough. The same tool will give you velocity, and what you need for input are board stack up and track width. You can tune that up and down to manually simulate manufacturing tolerances, if you want.

1a. You can use ATLC if you really think you want a field solver. It’s not hard to use, and it’s free. It will give you impedance and velocity, which is really all you care about in practical terms.

  1. Look at the IBIS model of the drivers for the two ends of the interconnect. You can calculate a driver impedance from that. Look up IBIS model to see what data there is in there, but a primer of what it tries to model is Basically, the data is piece wise linear current vs output voltage when driving.

  2. Draw out a typical interconnect. Source, driving impedance in series, transmission line of time delay (length, velocity), termination, parasitic capacitance of the input.

  3. Put that into a SPICE deck. It will be less than 10 lines of SPICE.

  4. Run a transient simulation.

This first order, lumped element simulation will show you what things are likely to look like, and let you find gross errors. You’ll be surprised how realistic the results look, especially if you get the parasitic capacitance at the input and transmission line (track) impedance close to right. You can model vias as capacitors if you want, just break the transmission line into segments (of the correct length) and put a capacitor to gnd. You might need a 1meg resistance to gnd also, or SPICE will complain about there being no DC path at those nodes… just anything large enough not to affect operation.

I’ve done this with SDRAM and LP-DDR designs, both in co-planer (that is, 2 layers with tracks separated by ground fill) and with multilayer designs. It works fine, the waveforms later validated by 1GHz bandwidth (not sample rate) scopes. Wave shape, undershoot/overshoot, damping, delay all a good match with the simulation.


Thank you very very much for a comprehensive explaination…