I am working with JLCPCB, they are complaining that I fail metal to metal clearance. KiCAD DRC is clean. The case they recently showed me is a via connecting to a pad. The outside of the via is closer than the rule from the pad, so they fail it. However, KiCad does not flag it, perhaps because the via and the pad are shorted together intentionally by a track.
My questions:
IS this a REAL manufacturability problem? My history is in IC design, such an error WOULD be a manufacturability problem in an IC layout because of the risk of an overly thin bit of photomask detaching and landing somewhere else. But is it an issue in PCB manufacturing?
Is this a recognized weakness in KiCAD DRC?
Are there any plugin tools or aftermarket tools that can help me find these, given that KiCAD DRC is not flagging them…so it’s hard to fix.
To be honest i do not know why manufacturers even specify pad to pad clearances at all. What matters is net to net clearance. As you noticed KiCad only checks net to net. (More is planned for future releases.)
The only reason why this could matter in this case is if the via drill is too close to the pad and therefore is able to steal solder paste from it. (As long as there is enough space for soldermask between the via and the pad or if the via is tented then this is definitely not the case here.)
Another option would be that the via is a red herring. Maybe the problem is that the trace is slightly too close. Could be a possible rounding error. (Slightly increase the clearance in kicad and try again.)
KiCad does nothing wrong here, this is just a normal connection between a pad and a via in the same net. I don’t understand why they complain about it. But you should be able to make it safe by using a wider track there, the same width as the via diameter.
The manufacturer definitely seems to be complaining about the metal to metal spacing, where both metals are the same net. They sent me an image, but it was a web link which has already expired, so I am afraid I cannot copy the actual complaint here. But the image had been annotated by them to show that it was an error from the outside of the via to the adjacent shorted pad.
BTW, they don’t check the KiCad design, they check the gerbers. Look at those carefully and with several gerber viewers, maybe there’s something wrong there. It’s also possible, though not probable, that KiCad has a bug in gerber creation.
Yes, I can easily fix it…on this individual case…how do I find ALL the errors without a DRC check to identify them? There are 3057 vias on this design, checking every one manually, on both top and bottom…is what I am currently doing.
Without a DRC check to find them, this is a slow and error-prone process.
We have ordered several designs from JLCPCB which were very tight, they had several similar pad/via connections with several track widths and lengths. Some vias were half on top of pads. We got no questions or complaints.
To be honest, it’s not an error. With this much information we have no idea what the real problem is. Maybe there’s someone incompetent working for JLCPCB. Or you misundertood their message.
Me too, I’ve never had such issues with JLCPCB in the past. It’s just with this latest design…wonder if they are using a new DRC checker…or new rules.
Depending on your design it might be possible to use track width for all GNDD which is as wide as the via diameter. In that way there won’t be gaps between vias and pads. You can edit them all in one go with Edit->Edit Track&Via Properties.
They are complaining about this all over the design,many MANY nets. Glogbal change of track width is absolutely NOT an option: it’s all/any net and global track width will cause shorts all over the design, the image I gave is an example. IF this is a legitimate DRC error, then KiCAD DRC REALLY needs to find it. If NOT a legitimate error, I’d REALLY like to be able to convince JLCPCB that hey are flagging false errors.
To pass the time between receiving incomprehensible emails from JLCPCB, I have been MANUALLY looking at all 3057 Vias and “correcting” this error everywhere I find it. I’ve spent over seven hours on it so far today, the “error” probably occurs on 25% of the vias…as it would…if the design is tight for space and DRC does not report it as an error.
Maybe you misunderstood. The image you gave is not an example of a situation where wider track would cause a short. If you would set the track width of GNDD - and only of GNDD - to as much as the via diameter it would depend on your design whether it would cause shorts or not, but in the image above it wouldn’t.
EDIT: do you have the same problem with other nets? It’s not clear to me. Of course the solution doesn’t work if many nets have the same problem. I thought this was mostly about a ground net because it’s common to have such short tracks connecting a pad to a ground plane.
No misunderstanding on my part. They are complaining about nets all over the design. Not just GNDD.
Because KiCad does not catch metal to metal spacing errors when the nets are the same as each other, the consequence of that is that there are such errors all over the design.
I cannot just increase track widths globally because the errors are all over the design.
I spent 2 days manually looking at every via and correcting every error I could find.
I re-submitted …AND… they are still rejecting the design for errors I cannot find.
I am HOPING they can send me a list of locations where they find errors so I can manually check and correct the last few.
In any case, it would be REALLY useful to have a more powerful and flexible DRC script I could run on the gerber, to look for these sorts of things.
It’s practically impossible that KiCad would make such big mistakes. Thousands of people make thousands of boards and send them to different manufacturers. Such a major problem would have been noticed before.
I’m not a “fanboy” trying to excuse by any possible means. I just can’t take as a realistic possibility that this would be a problem in KiCad. If I were you I would give up with JLCPCB and send the design to another competitor. They will probably be happy to make it without complaints.
(We have used JLCPCB without problems, but basically I don’t have 100% confidence on cheap Chinese manufacturers. There’s the language barrier and time zone difference which often makes communication very difficult when some problem arises. There are also cultural differences. People there must act as if they understood even if they didn’t so that they don’t loose their face. They may obey directions literally, but you never know whose directions and how they interpret them. Some young engineer may have had some orders which he didn’t understand but he can’t ask his superior for clarification.
I wonder why those manufacturers don’t put an option to their order page, “Don’t ask questions, don’t change anything if the manufacturing process and devices can take it, I’ll take all responsibility for all errors and mistakes.”)
Yup, I think I pretty much agree 100% with what you have written.
Ok, now to find a reasonable prices European vendor…I need 4 layers, 0.1mm trace width, 0.1mm spacing, 0.2mm via hole diameter and a limited number of controlled impedance lines, though they are not so critical that I need the manufacturer to keep it controlled…I just need to find a stackup that works.
I order at www.multi-circuit-boards.eu or www.pcb-pool.com
The later more for prototypes.
Both were reliable. pcb-pool seems to keep their PCBs back so they deliver at the date promised (say you want a 8 workdays board, it will take as long). multi-circuit-boards do deliver earlier (at least sometimes).
Multi-circuit-boards didn’t accept KiCAD files directly. But a few months after I requested that, they now both accept KiCAD! Juhuuuuu!
To your “problem” (better theirs). It looks to me, that they claim about an etching problem that actually isn’t one. You do have very narrow pointy gaps. And etching tends to have problems there. So the endresult would be a slightly wider track than you wanted. But I bet you don’t care.