I have a shared memory bus for a SRAM and a SDRAM, both have different bus pin definitions, so I can’t just use the same net names on both for overview reasons. So I ended up with something like this on the controllers end:
Is there any way to avoid the flood of warning this generates in the ERC because kicad decides which name it will use for the individual nets apart from disabling the check?
There is also an behavior which I do not understand: All SDRAM lines generate a warning for the SRAM bus, because they are graphically connected but not part of the bus (which is intended). However, none of the SRAM lines generate the same warning for the SDRAM bus, even tho they are equally connected. Why?
Because the SRAM labels are being ignored (which is the point of the other warning), those nets are only labeled SDRAM_* so they match up with the SDRAM bus and there is no warning for bus mismatch.
No, you have to either wire your schematic differently or ignore this warning (either in general, or for these specific cases using Exclude)
what exactly do you mean by this? The only option I see to get rid of the warnings rn is by removing the SRAM bus and decide on the memory side, which net to connect where.
You can right click on individual ERC violations and exclude them. Those will then be added to a list of exclusions and this list can also be revised / edited later. If you do this, you basically tell Kicad: “Yes, I’ve seen it and I decided it’s OK, so stop complaining”.
