Sensible rules for a 6 layer board

I have a project that has taken me out of my comfort zone.
I have a 6 layer power board in design, using:QFN-38-1EP smd controllers which need fairly small vias and via in pad.for cooling
The KiCad default 0.8mm pad, 0.4mm hole is way too big.
Any recommendations for a via size that most Class 3 fabs can easily make?
Also how do I do a resin fill layer in KiCad?

If you want to stay class 3 then you cannot have class 6 (0.2 mm) drill vias.

You are looking at class 4 minimum.

As for layers there are user layers (cmts, dwgs) and two eco layers. One of the eco layers should do.

Via in pad might be the “wrong” term to use for a via inside of the large smd pad. PCB manufactures use the term “via in pad (technology)” to rever to any technology that allows placing vias into pads where the via drill is a significant size compared to the pad (Example via in pad for bga pads -> copper filled small diameter vias)

Application note by TI (and others) might be good reads: http://www.ti.com/lit/an/scba017d/scba017d.pdf

TlDr: TI suggests via sizes of 0.3mm or less. They do not suggest filling because they deem it too expensive (I assume smaller vias are cheaper than filling them). Bottom tented vias seem to be problematic (leads to voiding. -> I fear the KLC might need updating because of that as we currently use bottom tenting for thermal vias versions.) Not sure how resin filled vias compare (is outgasing of the resin a concern?)

They clearly state if vias are >= 0.4mm then they should not be placed within the EP as this results in excessive solder loss (I would assume filling vias larger than 0.4mm with resin or metal should allow them to exist in there as long as outgasing is not a problem). All of that implies to me that <= 0.3mm via drill size should behave comparatively nicely even if left completely unfilled and untended.

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