Is it possible to send an entire bus to a sheet through one hierarchical sheet pin or do I really have to break out each of the 44 signals individually?
Yes, it is possible.
Thanks. I guess I should have gone on to ask, âhow do I do it?â Iâve done what I think are the obvious things and the signals are not connected through.
Yup, thatâs what I mean by doing the obvious things. Doesnât work. And by âdoesnât workâ I mean that the signals in the two sheets are not connected in the netlist. When I go to the PCB and import the netlist, thereâs no ratâs nest line where itâs supposed to be.
I thought it should work too so I still wonder if Iâm just missing something really simple. I can get single wires to make the transition to sub-sheets with no problem.
My signals are a processor bus, in fact theyâre the QBUS if youâre familiar with it. However, that consists of a lot more than just data[21âŚ0], there are all the assorted control lines, so for the purposes of your question theyâre probably more like disparate signals that I wish to group together.
If I recall correctly Eeschema supports homogeneous buses only (e.g. DATA[31:0]), it doesnât currently support heterogeneous buses (e.g. {DQS0, DM0, DQ[7:0]})
Well thatâs disappointing but, reading the manual, it does say that. That will make the schematic more difficult to draw, more error-prone, and much more cluttered looking. Too bad. Thanks to both of your for your help.
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Fell free to add your voice to this bug that asks for such feature:
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Please pardon the massive necro, but Iâm having a similar sort of problem. Iâm building a 65C02-based computer, and Iâm running the address and data buses out through hierarchical pins.
The ERC is telling me that most of the pins on those buses are unconnected. Iâve stuck a label on each wire saying which signal is coming out of the bus, and connected the bus up to everywhere it needs to go.
What am I doing wrong, and how can I fix it?
The buses themselves arenât labeled(they shouldnât need to be), but Iâve been calling the hierarchical pins ADDR_BUS and DATA_BUS.
As far as I know, KiCAD still doesnât support doing what I wanted to do. Iâve since broken all those signals out into individual hierarchical pins and that works. However, grouping numbered address and data signals together did work for me so offhand Iâm not sure what youâre doing wrong.
That feature with mixed bus signals would be very handy. @David_Bridgham have you raised an issue for that feature?
Ciomaâs reply has a link to the bug report that was posted almost 4 years ago. I see that its status is listed as âin progressâ and the latest message there, only last month, suggests that this fix may finally come along with v6.0. I hope thatâs so.
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Wohoo! Thanks for that great news!
See this video that was released soon after the initial release of 5.0. Yeah, most of it is asking for donations (the donation link in the youtube description isnât active anymore, use the donate to cern button on the main kicad website if you want to donate), but there are some quick shots of what is in development for 6.0.
For the enhancements of busses see 0:44 in the video.
Unfortunately soon after 5.0 was released there was a major issue with the version of one of the dependencies being disabled in many Linux environments so 6.0 development was back-burnered until the dependency was upgraded. We all hope that once 5.1 is released development on 6.0 will resume.
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To my own experience , Itâs possible, you just have to name both your hierarchical pin and the bus in the same BUS[0âŚ15] style. like this:
This is what we get with a 2x2 years old threadâŚ
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Closed as this thread is to old and will only confuse users of newer versions of kicad.