I just looked at your file again.
Another very unlikely source could be your symbol.
You named your pins in unit a and b the same.
maybe name them ch1+,ch1-,ch1_out
(I’m clutching on straws here. I never experienced such a weird behavior.)
@kaitrek, please check your opamp symbol against pin overlaps. Someone might hide common pin 1 in unit B or common pin 7 in unit A, because didn’t know how to edit pins in the right way in multi unit components.
Load symbol to library editor and perform basic check (ladybug icon).
Pin names don’t matter I think, as long as pin numbers are different.
Like I said, when I had one CH1, there were no errors, when I added CH2 and CH3, I started getting these errors.I just searched for the “net 4” and I keep finding the same net in different sheet names CH1/2/3, which is wrong, hence the error ERC throws out.
Providing the whole project would be tough, have not played with ways to export custom components along with the project yet. I was just trying to reproduce the error with LT1492, just the input-preamp section with 2 channels, but I’m not getting the error. I’ll keep trying to narrow it down or reproduce.
Yes, I have re-annotated the entire schematic, otherwise I’d get multiple components error dialog before ERC is completed.
Good catch! By the time that screen shot gets to my laptop screen, the colors are rather muted and smeared so the error was hiding in plain view.
I vaguely recall that somebody suggested an alternative color scheme about a year or 18 months ago. One of the objectives was to make connections (or lack of connections) more obvious, but I thought the bright, neon-like, colors created more eyestrain for the 99% of the time when you are NOT looking for errors. In EESchema you can experiment with color schemes using the “Preferences” > “Schematic Editor Options” > “Colors” menu.
I will give you credit for presenting a challenging case. Every few weeks somebody brings a problem that boils down to lines that appear to be connected, but actually aren’t. (Grid size mismatches, and lack of dots indicating junctions. are the usual suspects.) This is the first time I recall having an extra connection!
I cannot think of a situation where a wire segment should be allowed to overlay a symbol box edge.
I have made this mistake once and its hard to spot, impossible in a black and white print
That’s quite true if you persist in the idea that a schematic must be human-readable and human-comprehensible. With this assumption information is lost when one line obscures another
If you define the schematic as a method of defining the components which make up a particular electronic circuit, and describing their interconnections, then colinear segments are a lesser problem. In the example we’re considering here, there is no problem because the line representing a wire (or connection) is an entirely electrical concept; while the line marking the edge of the functional block’s symbol has no electrical significance whatsoever.
I don’t know if it would be practical to identify this situation during drafting and issue a squawk since the condition occasionally happens as you move things around in the drawing. (And, hopefully, you promptly locate and correct all of these errors.) It would be helpful to include this type of fault in the DRC, with an error message something like, “Portions of the Net nxxxx connections are inside a component symbol at {X, Y}.”
I’ve seen a few, mostly in the world of logic, that are essentially just that: many components, arranged neatly on a page, but with very few actual connections shown. Instead, every pin was labeled with a signal name. Essentially impossible to comprehend the relationships between those signals.
That sounds like it came from the wire wrapping era. When one of these boards was built it was almost impossible to trace the wiring by eye and all you could do was buzz it. I am really glad wire wrap has gone away
Also could control line width individually. Have global presets for wire, bus, polygons, and text. Then also have control over individual placed elements that would override global control, or sheet control.
I think the most recent builds include net highlighting in eeschema - selecting a net with the label tool will highlight the whole net. Not certain when this was added.
