Hi,
I modularized my project so that I can make one schematic and use a single schematic for multiple audio channels.
See here, I have a single file, that’s used 3 times. Each sheet name is unique otherwise problems arise, and then each component ID is unique inside the sheet. CH1 will have diff. comp.ids than CH2.
As new user, can only post 1 image, so I combined them. TOP is the top level schematic, bottom is the Input-Preamp CH1 schematic.
KiCad needs to be smart about that, otherwise what I’m trying to do, which is the purpose of hierarchical sheets, cannot be done.
If I change the top level labels to R1 and L1, then ERC complains that there’s a pin mismatch, rightly so, names do not match, when I go inside and change CH1’s R to R1, CH2 sheet will also have R1, so how am I supposed to use the same schematic for multiple channels to have different outputs?
No that’s how hierarchical sheets are used.
If you use the same file for multiple instances you can’t change the names of the hierarchical labels. The only thing that is different in within this sheets is the reference designator.
I think the problem is within the sheet volume pan stereo.
Can you give us a screenshot of that sheet? (maybe there is a connection between the R/L channels.)
(Or your project files,)
Also check if there is a connection between the global label V- and feedback loop.
I checked pan-vol sheet by disconnecting the R and L channels, the error persisted, that means the input-preamp sheet is the sole problem.
If I disconnect pin 7 from L pin in the input-preamp sheet, then all errors go away, but then I am missing left audio channel.
I did not have this error when I only had one channel, CH1. It only appeared after I copied and added CH2 and CH3 by holding shift then click drag select then move and release to copy the sheets, maybe this created a problem in KiCad? Should I have created a new sheet with the same filename and populated the pins, maybe the copy didn’t write something correctly in .sch?
There is no connection between V- and feedback loop, there is no junction there.
I always do it this way. Never had a problem.
(I even tested it right now with a simplified version of your schematic. Had no problem.)
You could try to delete ch2 and ch3
Than don’t copy it as you did before but create a new hierarchical sheet with the same file name as the one you use now. There should come a warning.
[A file named ‘[filename].sch’ already exists in the current schematic hierarchy.
Do you want to create a sheet with the contents of this file?]
Click yes and reconnect it.
Maybe this solves the problem.
I just looked at your file again.
Another very unlikely source could be your symbol.
You named your pins in unit a and b the same.
maybe name them ch1+,ch1-,ch1_out
(I’m clutching on straws here. I never experienced such a weird behavior.)
@kaitrek, please check your opamp symbol against pin overlaps. Someone might hide common pin 1 in unit B or common pin 7 in unit A, because didn’t know how to edit pins in the right way in multi unit components.
Load symbol to library editor and perform basic check (ladybug icon).
Pin names don’t matter I think, as long as pin numbers are different.
Like I said, when I had one CH1, there were no errors, when I added CH2 and CH3, I started getting these errors.I just searched for the “net 4” and I keep finding the same net in different sheet names CH1/2/3, which is wrong, hence the error ERC throws out.
Providing the whole project would be tough, have not played with ways to export custom components along with the project yet. I was just trying to reproduce the error with LT1492, just the input-preamp section with 2 channels, but I’m not getting the error. I’ll keep trying to narrow it down or reproduce.
Yes, I have re-annotated the entire schematic, otherwise I’d get multiple components error dialog before ERC is completed.
