Rule checker and vias

I placed a via with pad diameter = 1mm, hole diameter = 0.75mm. Now, the minimum trace width is 0.16mm. Notice that for the layers where the via connects to nothing, the via ends up creating a “copper ring” where the copper line is 0.125mm wide, which is below the minimum width.


  • Is that a problem? (I think it is — that is, if we consider that the minimum copper width is 0.16mm, as I think it should be)
  • If it is, why doesn’t the rule checker flag an error or even a warning?
  • If there is no way to have the DRC detect this, is there a way for me to verify whether I have vias with copper ring below the minimum trace width? (I fixed the one, but then I’m not sure whether there are more like this one)

I guess my doubt boils down to the issue that the design rules allow me to specify a minimum trace width, and not the more general notion of a minimum copper width. (correct?)

Notice that I did that by mistake — the via connects a ground zone (set to “Solid Connection”) on the top layer to the ground plane (also a solid connection). What I overlooked is the other layers, where the via actually connects to nothing.

Any thoughts? (EDIT: aside from the fact that a search for the regular expression via.*size.*drill 0.75 in a text editor helps…)

Plated holes typically have their own rules given by the manufacturer. Search for minimum annular ring requirements on the manufacturers capabilities page. If the manufacturer does not give this information then you need to check the drill tolerances and drill to copper alignment tolerances as well as the plating thickness to calculate it your self. (I would much rather ask the manufacturer for clarification than to calculate it my self to be honest.)

Sadly kicad right now has no inbuild annular checker. But there is a script out there that can help (Not sure if it works on current versions of kicad) Annular checking: How do I check if all my pads diameter is drill diameter +0.3 (or so)?

I am not sure how this applies to layers where nothing connects to the via or pad.

Thanks Rene_Poschl. The manufacturer (Seeed Studio) only specifies “Minimum trace/space”, and it shows 6mil/6mil at their default settings/pricing. My assumption has usually been that I should also apply that constraint to the width of annular rings.

Good point, I guess — the minimum width ensures that the trace is not damaged, compromising the connection; but if it doesn’t connect to anything, then nothing gets compromised.

As you recommend, best to check with the manufacturer.


Annular ring width works differently than track width. Minimum track width comes from the etching process. Vias are by nature wider (diameter is more than track width). They are round copper pads which are later drilled through and the hole is plated. What counts for annular ring is that when the drill hole placement is wrong the ring edge may break. Even that isn’t necessarily bad in itself because the other side of the ring compensates it. However, if the drill hole is on top of track which leaves out from the via the track will be cut. (That would be one good reason to have teardrops in KiCad.)

The majority (not all) board manufacturers seem to have the same requirements for annular rings as for general trace width. Some require annular rings to be wider than traces - possibly to allow for drill diameter tolerances, as well as locational uncertainty for the drill hole.

Seeed Studio has my admiration and respect for publishing (at no charge!) a rather comprehensive guide to PCB design requirements. You may download a copy at “PCB Design for Manufacture” . When the document mentions specific numerical values, they seem to be the current requirements for boards fabricated by Seeed Studio; I don’t know how conscientious Seed Studio will be about updating those values as requirements change over time.

In Section 10.1.1 of that document, on page 20, the topmost sketch in Figure 26 shows a 6 mil annular ring. I couldn’t find a specific discussion of annular rings, but trace widths (in general) are discussed in Section 7.1 on page 12.

I agree that the DRC really should check this. (I have no appreciation for how easy, or difficult, it is to program such a check into the DRC.) In my opinion, the DRC in general is a weak point in KiCAD. I would prefer to have development resources directed toward improving DRC rather than, say, interfacing to autorouters or SPICE simulators.


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