Routing Complicated Netlist

Hey guys,

First of all im not sure which topic is this but now i choosed Layout 3D Models Thema. Correct me if im wrong.
Actually here i want to ask for Advice.
So i have here a ADC component called DDC114 and a MCU Adafruit feather rp2040.
I want to make a test setup.

So i made this eeschema and assign all the component with the footprint.

I come to build and routing the netlist.

But apparently everything seems so mixed up. If i make one route, it will block another route and i cannot route it.

Specific area

I cant change the DDC114 pin like what i did in the eeschema.

Is there any advice for this things?

Thank you and appreciate all the helpers :slight_smile:

Arrange the items that are fixed in position and pinout, then try to find optimal placement that will allow for easiest routing. Good placemenent is more than 50% of the whole success.
Then route the nets according to many rules. You can use multiple layers if you can’t avoid nets crossing.

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There are a variety of ways to do routing. First, you seem to be quite new at this. You can use the front AND back of the board to route. You can sometimes place components so they go over a trace to act as a jumper. You can go 4 layer if that isn’t enough. Check the FAQ section and look for the tutorials.

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I think there are several problems here. It is hard to see. Is +5V connected to GND?
U3 will not function like that.
These parts need to be close to U1.


I am designing 2 layer PCBs with whole bottom destined to GND so I have only one layer for all my connections (except GND). How to avoid crossing wires is the main problem I have to solve with each PCB. To get this I frequently change microcontroller pin assignments. To make switching currents smaller I like to use at each digital output pin the 47 ohm resistor. These resistors also help to cross signals. Sometimes I also use 0R (0603, 0805, 1206) to jump over several tracks.

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This is actually a very simple PCB, and learning how to deal with the crossing tracks is an important part of PCB design.
If you have a look at a few of the projects in: you can get an idea of what a more complex PCB looks like. I particularly like the OlinuxinoA64. Full KiCad project is on Github, but the KiCad projects of all the other PCB’s mentioned there should be easily obtainable.

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thanks for the correction :slight_smile:

i did it now. thanks.
But now i got a new problem. After i routed everything and run the test, all the nets are connected but i got a problem with pad too close to pad.

And actually the pad wasnt made by me. i just used someone footprint.
i tried to change the clearance and run the test again, but i didnt work.

any other solution?

thank you :slight_smile:

thanks for the advice. i used 4 layers now.

Everything is now good with the routing but now i have new problem because there are some error said pad too close to pad. i actually use the footprint from TI instrument for my DDC114 component and i dont know how come there is this error…

i tried to change the clerance and it didnt work.
Any idea ?

thank you

You need to review your design rules, to check if the minimum clearances you did defined (File > Board setup > Design rules > Net classes) are set up right.
Check with your board house what are their limits, and keep within these specs.
Four layers is probably overkill for a rather simple board, but it’s easier to route it using 4 layers than using only two.
If you feel you want to stick with 4 layer design, use proper layer stackup and use copper planes for you power and ground.

By the way, you have your +5V and GND nets shorted in two places on your schematic. At least on the schematic published in the first post, above. One place was pointed out by @ronsimpson, above your U3, and the other (that I found) is at the jumper off of JP1-3. As a result of that power net short, on the routed section that you showed of the pin 12/13 corner of your U1 chip all the grounds are connected to +5V net.
(KiCad only supports one name per net, and in this case the +5V name happened to win out over the GND name.)

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