Request: Filled zones with boundary clearance

Community Feature Request Chat
1

I do have a suggestion for filled zones. I stumbled over this problem a few days ago.
Let me start with an example that is trivial and would not justify this request. But it makes the case clearer.

Often enough, you have zones, that do represent completely isolated regions on the board. For example on an SMPS. One side is mains, the other side is power output. Or a µC controlling mains over opto-couplers.

obvious
obvious940×1082 112 KB

This example is quite obvious. We need isolation between N and L1 (left side of the layout). So the isolation is set to 0.5mm (all on layers 2 and 3). Then there are 3 opto-couplers bridging the gap between mains and the controlls and an AC-DC-converter. It is a no-brainer to make that isolation gap as big as possible, at least using the OCs as guide. But this also already makes clear, that the isolation gap on top and buttom layer need to be bigger than on sandwitched layers.

Now to a more useful example:

clearance
clearance725×847 81.5 KB

It is an isolated USB-interface (IIRC 1 kV). The voltage difference within the highlighted area is 5V. So clearance within the zone is 0.2 mm and enough. But the clearance to any neighboring zones needs to be way bigger. And it isn’t in this example. I simply forgot about it. :frowning:

So my suggestion is, that zones should have an extra parameter “boundary isolation”. By default, it is chained to “isolation”, but can be unchained and set to say 2 mm without affecting isolation within that zone.
By “chained” I mean something like this:
linked
You can click on the chain, and then assign a different value to the boundary isolation. A check box would work too.

There are other examples, where isolation is more embedded within a PCB. For me, that is often RS232 or RS485.

I hope, I made my point clear. If not, feel free to ask!

So, is that a stupid idea, am I just to lazy to adjust the gap manually or …?

1 Like
2

I think this is an important topic.

Another use case is where one might have a high-side gate drive in a power half-bridge. In this case, the gate drive components are low voltage and have low voltage (<= 15 V typically) between any other gate drive components with the exception of the level shifter that communicates with the controller. However, the group of high side gate drive components must have sufficient clearance to all low side components, which in some designs could be at a potential difference of several hundred volts or higher.

I do not yet have much experience with KiCad, but in Altium I do this by assigning a net class called “HS_gatedrive” to all components that are in the high side gate drive. I use a blanket so that I can do this as a group on the schematic. Then, I made a rule that anything belonging to this net class must have “x” clearance to any nets not belonging. If the polygon (zone) that needs the larger clearance is assigned a net that belongs to the net class HS_gatedrive, it will have “x” clearance to any components not in HS_gatedrive.

It seems like this should be possible with custom rules in KiCad as well.

Hope this helps,
John

3

The current workflow to solve this issue is to utilize custom rules.

My workflow would be:

  • assign all nets on the isolated side to a netclass “usb_isolated”
  • then use a custom rule for clearance between “usb_isolated” and any other netclass

Examples for such clearance rules exist (either in the custom rules help dialog itself or as examples on the kicad pcb manual).
Your approach is useful only for limited usecases, while the custom rule solution is very flexible.
Admittedly these custom rules need some time to get used.