Remove soldermask on Vias

I need to remove the soldermask on the Vias, but the build in function (“Remove soldermask on Vias” checkbox in the gerber plot dialog) has no options. Is there a way to get vias with defined soldermask expansion (IPC recommends drillsize + 0,15mm)?
I am using kicad 2015-02-28 BZR 5464

There is only “Do not tent vias”, nothing else.

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Agree with @madworm, I don’t know of any other ways of affecting via soldermask. I’m more curious about the reasons behind that IPC spec and how other programs handle this.

The reason is that you don’t want vias covered with solder mask (for reliability + production issues), but the hole in the solder mask should be as small as possible to minimize the risk of shorts on the exposed copper ring.
In Altium Designer a via is handled in the same way as a pad. You can specify the solder mask expansion (positive or negative) for each via or globaly. I really miss this in Kicad.


As far as I can tell, the “do not tent vias” option produces a hole in the solder mask of the exact via size. Is it really that different from what the IPC asks for? If yes, how much this changes the “reliability and production issues” and why?

And by the way, what prevents us from defining the via size exactly as drill size + 0.15mm (or should it be drill + 2 times 0.15), this way the Kicad’s solder mask hole will be spot on IPC spec :wink:

The IPC / ZVEI recommendation (Drill size [NOT hole size] + 0.15mm) is not written in stone and there are other “rules” (for example Hole size + 2x 0.15mm)

I’m working with a fairly ancient version, but I’m seeing the option to change the mask expansion under Dimensions -> Pad Mask Clearance. If you set that, and then use the “Do not Tent Vias” on the plot page, then it will generate the specified mask expansion around your vias. It shows these settings on the Plot page too. Strange you can’t set them from there though.

For your case though, it sounds like you’re wanting the mask to cover part of the annular ring, but not over the drilled hole. You could set the mask expansion as a negative value (like Annular Ring -1.5), but that screws with all your SMD pads too. I think you’ll need to go out of KiCAD and fiddle with the gerbers directly, but shouldn’t be too much trouble.

The easiest way I can think of is to do the following with the help of GerbV (not Gerbview, which comes with KiCAD)

  • Export the gerbers and NC Drill file
  • Open the NC Drill file in Gerbv
  • Go to File >Export RS274X (Gerber), save it as something like mask-holes.gbr
  • Open mask-holes.gbr in a text editor, and add 1.5 mm to each expansion. If you’ve never fiddled with gerbers before, the line looks like this:%ADD13C,0.01*% , with the number after the comma indicating the size (Usually in Inches. In this case, 0.01").
  • Using GerbV, open up mask-holes.gbr and the drill file. You should see the nice expansion. Close this, or correct anything you need.
  • Open up mask-holes.gbr and the top mask layers. Go to File > Export RS274x (Gerber) Merge, and save it as the top mask file.
  • Repeat for the bottom.

Done! If you’re on a command-line friendly system, you can replace a couple of these with GerbV’s helpful command line options as well. If you’re having to re-plot a bunch of times, probably not a bad idea to script it.

I’d like the same thing as the original poster. This is recommended with the ENIG finish to avoid trapping chemicals in the vias.

The image below is what the 3d viewer shows and what I want. The mask openings are not in the gerbers. (Kicad from yesterday’s BZR).

This is what I get if I check “do not tent vias” exporting gerbers. Completely useless in a 0.8 mm pitch BGA. You don’t want the BGA balls getting sucked down the vias.

I tried the gerber hacking suggested by tekdemo and it works. It would be nice to have this as an option in export gerbers, or even better, parameters to edit on vias like Altium. I already have to edit gerbers on this board to get 0.45 mm outer layer and 0.5 mm inner layer via pads (Eurocircuits finest design rules, need the smaller outer pad to avoid shorts under the BGA).

I think that is a render-error when “copper thickness” is turned on.

It would be indeed a very useful option for me to control solder mask on vias on a per-via basis, ideally with separate options for top and bottom mask layers.

By default I have them tented. But for some I expose only the drill, for others I want to expose the drill and annular ring. Rarely I want to expose the back side e.g. as testpoint, while the front should be covered because of nearby solder.

What I think I have to do in Kicad is to create the corresponding circles for B.Mask and F.Mask and paste them over the desired vias. This is not too complicated, but would be easier if it was just an option for the vias themselves.

7 year old thread. Much has changed.