Have designed a PCB from a multipage schematic, using V7, and everything looked OK. PCB do chek out with zero errors at DRC. But after receving the PCB from maker, I realized some nets did not match my schematic says.
The schematic was created by cut-n-paste an old design, but new nets were defined. Still the “old nets” seems to take priority, and no matter how I try to update the PCB it refuses to correct this. After deleting the tracks, deleting the nets in schematic, then update PCB, rewrite schematic, and update PCB with the new nets, it totally confuses the PCB and now seems to pretty much combine all these nets into one.
Is there a way to force the nets in schema to update my PCB??
Welcome! That does sound very frustrating. I don’t have a specific answer for you with the information given, but it seems like the kind of thing that would be easier to help with if you can provide the actual design files in question. (Or delete some sections of the project while still showing the issue if you don’t want to make the whole project public). Alternatively, if you can include some detailed screenshots of the pasted schematic and corresponding layout, that may also help.
As you are a new member, you’ll probably need to spend some time clicking around for the forum software to make give you attachment privileges. This link has more details: New Member Information
and this connects to:
See next posting as I cannot post two images in one post…
There are 16 similar output circuits, and it is the signals controlling these that are messed up, signals 10dB_A, 20dB_A, 40dB1_A and 40dB1_B are correctly drawn in the schematic but magically ends up at the wrong place, i.e. 10dB_A ends where 40dB1_A should be and so on.
It reflects how my old schematic was drawn, but why does the PCB refuse to update to the new configuration?
And here is a grab from the PCB, which has been autorouted and postprocessed. If I remove the tracks and try to update using F8, nothing changes. Notice that the net is 10dB_A and routed to U11 not U9 which is specified in schematic
The little squares indicate open wire ends, and the slanted wires are also longer then the Wire to Bus Entry. In later KiCad versions (I think both V6 and V7) have become much more then in the old KiCad, where the blue bus lines were just graphical and KiCad relied on local labels for the connections. With this new system, you can also connect a bus to a hierarchical sheet directly, instead of breaking out all the bus wires and using hierarchical labels on them.
I can not deduce much about your wiring problems from a few screenshots. Are you able (and willing) to zip up and upload (at least a part of) your project so we can look at the project itself to diagnose it? At the moment you have not reached the required “trust level” yet, but you’re close.
Wow, some eagle eyed!! Thank You, really appreciated, makes me realizes I’ve really made some really stupid errors, guess I have to live up to my “nick”. I hope I’ve fixed the bus naming and re-attached labels. Now I stared a new project, and just copied the updated schematics, and exported to a “blank” PCB… and to my surprise I still get the nets misplaced. It is “10dB_A, 20dB_A, 40dB1_A and 40dB2_A” that ends up tied to the wrong chips. There are zero errors nor warnings.
I see you’ve been tinkering a bit with the schematic and added the bus breakouts. It still should have worked with just the local labels though. That was not the real problem.
Your project is missing the PCB, and without the PCB we still can not see why the linking between the schematic and the PCB does not work for you as it is supposed to work.
As I wrote, if one create a PCB from the attached shematic, the nets does not match!
This pic just shows how net 10dB_A is connected to U11/U15 which does not match schematic. I did save the PCB and exported an archived project, if this helps.
The net name 40dB1_A is local to the subsheet but it’s connected to a wider net, the net isn’t really local to the subsheet. KiCad uses only one net name for each net and chooses the final name according to some rules. It’s natural that the name in the higher level wins.
Then I saw your attenuator schematics were both the same. This is an enormous amount of extra typing, or at least it leaves in the possibility to create more errors. So I renamed one of the sheets to “Attenuator”, and removed (Yes, I deleted it) the other.
Then I modified the root schematic to both directly connect the buses, and to use two instances of the same sheet. It looks like this:
Last, I simply deleted all parts on the PCB and re inserted them. It is possible to re-link, but as the PCB was still empty, this was the simplest.
So here is your cleaned up project back: 2023-10-17_test_2.zip (112.8 KB)
D’oh! Who to blame, looking in the mirror.
On a serious note not sure when this happened. Likely it due to my mistakes with using buses eronous, as this is not how I did specify the labels in the first place. Still I am really greatful for your help. And hopefully this made me understand a bit more about labels and hierarchical pages.
Cheers!
Wow just noted your last posting! Ever so grateful for your help, trying to help a Simpleton!
Will have to start trying to fully grasp the concept tomorrow, as we are past midnight here.
Thanks a million!
On the attenuator sheet, the wires with the same labels are also connected (although they should not) while the wires on the CPU sheet are not connected to the attenuator sheet instances at all.
It took me (quite some) time to get it correct. My previous example was screaming a lot of ERC errors at me, but I was to ignorant, hasty or forgetful to even check it.
When you want to use buses like this, you have to be careful with the bus names, hierarchical labels, and how everything propagates though the hierarchy. The bus type used is a named group bus. In such a bus you have to name both the bus itself, and the bus members. For the bus members I changed the “Attenuator” name into the shorter “dB” (mostly with Schematic Editor / Edit / Find & Replace) and I used the same alias definitions as a list of dB attenuations.
Another error of attempting to be too quick was using a wire in the root sheet to connect buses. Duh!
Also note that the real net names (on the PCB) are now derived from the bus names in the root sheet. there is an AT1 bus and an Bussy bus (both with attenuator members).
And as with all free work, there is no guarantee it’s fit for purpose or that it works at all. So make sure you check everything works properly before you continue. Using both the net higlighting and the ERC are good tools. Also use the cross probing by having both the schematic and the PCB editors open at the same time.
And last, you do not have to use both local labels on the bus itself and an hierarchical label. If you just use a hierarchical label such as AttA{dB} on a sheet, then the bus foldout works too (if the list is already defined of course).
Paul, a big Thank You for digging into my problems. The issues in my original post is understood and fixed.
Now I’m trying to figure out how the bus and hierarchical labels work, this will take some time and tinkering. Just for fun, I took my PCB design into your refined project and updated the PCB using the “new fixed schematic”. Oddly I get heaps of net errors, my understanding; wouldn’t the nets just be renamed, and the layout stays the same? Apparently not so, and I have to start play with defining the buses between hierarchical schematics. Not sure though how much time and effort I can throw into this now, as this is just icing on the cake and there are other projects waiting
A part of the reason I did it is to update my own knowledge of this part of KiCad. I do not use buses much myself, and need a reason to practice a bit with it.
One problem with doing this with an existing project is the removal of complete schematic sheets, and using two instances of the same sheet. This breaks the links between the schematic and the PCB, and because both the UUID’s and the Refdes are broken, it is time consuming to fix. The easiest way to fix it is probably to remove all the footprints from the PCB of the “new sheet instance”, and then replace them with newly imported footprints. You can get the location back by snapping a pad of a footprint to an endpoint of a track.
For you it is probably easier and better to just fix the few accidentally swapped labels, and then use this method for your next project. Also noteworthy is the Replicate Layout plugin. It works on hierarchical sheets like this. With the Replicate Layout plugin, you can draw the Part of one schematic sheet on the PCB, and then replicate that layout for the other (identical) sheets.
And hopefully this made me understand a bit more about labels and hierarchical pages.
