Does anyone have info on the [rebuild board connectivity] and
What it requires to start ? Does it also need/read a NET file ?
What does it report as it runs ?
What is it trying to do ? / What rules does it apply ?
I have a PCB with net-names in PADS, and traces with no-net tags, and some tiny percentage I think may have updated - but I saw no messages. (testing in V5 rc)
Broadly, I was expecting a button called [rebuild board connectivity] to do something like this
Find PADS or trace segments with netnames.
If any ‘floating’ Net trace connects (same XY as corner) to an element with a valid name, then apply that name.
As another test, I take a simple free trace segment (no net), and carefully move to have corner XY over a PAD/trace, and try combinations of load/save/import/[rebuild board connectivity] and nothing ‘connects’ it.
[rebuild board connectivity] seems to take no time and report nothing, so it’s not even clear it does anything ?
I’ve never felt a need to click that button. It took me 5 minutes just to figure out it was in the Netlist window.
I’m not certain, but I think the Netlist “feature” is going away in the future.
Since you state you are using a V5RC then I recommend you use the tool “Update PCB from Schematic” instead of the Netlist feature. I’m also using a V5RC2 version and I encountered an issue where the Netlist and the new tool were not in agreement with each other; and until I used the new tool the Footprints in my design did not populate properly.
The tool-tip on mouse-over reads, “Rebuild the full ratsnest (useful after a manual pad netname edition”.
Hehe, well, in this case, there is no SCH
I’m testing flows from scripts, and in this particular test case, I’m testing GerbView ‘rebuild’ of a design from Gerbers.
What I have found is
Starting with a ‘99% correct design’, adding a trace polyline, and moving that to intersect with an existing net, is actually quite auto-connect-smart. It does not need to ‘corner match’, it just needs to be either inside the PAD outline, or inside the trace segment, and it will ‘auto-tag’ with the net name.
The from-GerbView design behaves very differently, refuses to autotag in any test.
The only real difference, is the from-GerbView has ~ 5% valid nets, and 95% (net 0) - all I can think is PcbNew has some threshold above which some features ‘give up’ ?
I am attempting to nail down just when and how PcbNew handles auto-reconnect.
The [rebuild board connectivity] sounded promising, but the hint of “Rebuild the full ratsnest (useful after a manual pad netname edition” is not any help.
I can only think they meant ‘edit’, not ‘edition’, but it seems to do nothing ‘extra’.
With more tests I have found that file load does itself have some inbuilt [rebuild board connectivity]
eg I can take a PCB file, and detach all net tags from vias and traces on some 500 lines, and then load that with the NET tags still intact on the PADS.
That test case, does seem to [rebuild board connectivity] automatically on load. No extra button needed.
Move and release of a trace polyline, seems to also do the same [rebuild board connectivity] - now I have to figure out why one (segment…) design file is OK (smart),
Yes, that’s the puzzle - there must be some other detail in the file that triggers this, because the segments look identical to me…
Digging deeper, I’ve found a trigger, it is a rule the hidden auto-connect uses. (irrespective of DRC)
If there is a violation ( I guess ambiguity) the auto-connect fails.
In this GerbView generated design, removal of edge-copper auto-connects 95% of traces.
The remaining ones will auto-connect on via-move (or delete), but only some vias trigger/need this.
Close checks show GerbView added vias that trigger other side violations are the fail ones, all others are tolerated.
Autoconnect seems quite ‘live’ - as soon as via centre is no longer within PAD, it connects.
No button needed.
Note this is also outside UNDO, and undo to replace the via, does not undo the connect net name - minor point, but it makes testing harder…
Very good question. Looks like they are somewhat similar, in that the (old) issue #1 in that thread looks to be the load losing some net associations.
The newest versions seem quite a bit better, plus the Hidden Autoconnect looks to be live, and quite smart.
I tried the example issue #1, and isolated a via + track inside a plane area - that saves/loads just fine, preserving the net name ok. ie it does not lose net-names, even if isolated
Hidden Autoconnect is slightly different/smarter : it will try to apply a net name to any (net 0) item, if it can.
It does not need strict XY centre align, ‘end point inside’ is sufficient, but it does not like violations (DRC off is ignored by this alogrithm).
That’s good news for importing designs via gerber, and with the new manual Add-Netname features in this WireIt thread mention
Someone can import gerbers int GerbView, Save as PcbNew, (ideally without vias) then add parts manually to correct XY, and then manually add the netnames, using WireIt
As valid Pin/(Trace)/Netname sets are found, they will auto-connect to the imported trace polyline.
With care, you can never see a ratsnest
The rule means once all pads are named, the trace polyline will auto-connect. A single renamed pad is not sufficient, because the trace polyline has a violation on the not-yet-named pad(s).