Reading third-party netlist into PCBNew - no ratsnest

I have an interesting problem. I have created a netlist (in KiCad format) from another schematic entry tool. I have no library references in the netlist and have all footprints assigned. When reading the netlist into PCBNew, all the components footprints show up, no errors are reported but I get no ratsnest! In fact the stats at the bottom of the PCBNew window say I have 154 Pads and only 1 Net.
I am not sure what I am missing since the footprint assignment and connectivity are in the netlist, and the footprints in PCBNew have the component pin assignments.
Before attempting to bypass eeschema, internet searches turned up a few other people creating “third party” netlists and going directly into PCBNew for layout and routing. I already have a schematic capture tool that I have been using for a few years and have developed a library and some scripts that are quite productive for me. The documentation doesn’t address this methodology. I am using KiCad v 4.0.5.

Any ideas what the problem may be?
Is there any Dev documentation that I can access that might give me more insight into this problem? For example I assume that there is some sort of netlist representation within PCBNew, perhaps in a database… how is this created from the netlist that is read in (usually from eeschema)?

Here’s a clip (not the full netlist) from the netlist:

(export (version D)
  (design
    (source C:\Users\Bob\Documents\Schemtic.dat)
    (date "Wednesday, December 21, 2016 3:01 PM")
    (tool "Schematic_Entry_Tool"))
  (components
    (comp (ref C1)
      (value 1000pF)
      (footprint R_0603)
      (fields
        (field (name "Part Number") 06031C102MAT2A)
        (field (name Manufacturer) AVX)
      (Date June 18 2000)))
    (comp (ref C2)
      (value 10uF)
      (footprint C_2220)
      (fields
        (field (name "Part Number") T521V106M035ATE120)
        (field (name Manufacturer) Kemet)
      (Date November 30 2015)))
    (comp (ref J1)
      (value XXX)
      (footprint bornier4)
      (fields
        (field (name "Part Number") )
        (field (name Manufacturer) )
      (Date December 13 2016)))
    (comp (ref J2)
      (value XXX)
      (footprint bornier5)
      (fields
        (field (name "Part Number") )
        (field (name Manufacturer) )
      (Date December 13 2016)))
    (comp (ref R8)
      (value 10K)
      (footprint R_0603)
      (fields
        (field (name "Part Number") ERJ-3GEYJ103)
        (field (name Manufacturer) Panasonic)
      (Date October 7 2015)))
    (comp (ref R9)
      (value 10K)
      (footprint R_0603)
      (fields
        (field (name "Part Number") ERJ-3GEYJ103)
        (field (name Manufacturer) Panasonic)
      (Date October 7 2015)))
    (comp (ref R10)
      (value 10K)
      (footprint R_0603)
      (fields
        (field (name "Part Number") ERJ-3GEYJ103)
        (field (name Manufacturer) Panasonic)
      (Date October 7 2015)))
    (comp (ref U5)
      (value XXX)
      (footprint SOIC-8-1EP_3.9x4.9mm_Pitch1.27mm)
      (fields
        (field (name "Part Number") PIC12LF1822-I/SN)
        (field (name Manufacturer) Microchip Technology)
      (Date December 13 2016)))
    (comp (ref U6)
      (value XXX)
      (footprint MSOP-10_3x3mm_Pitch0.5mm)
      (fields
        (field (name "Part Number") ADG704BRMZ)
        (field (name Manufacturer) Analog Devices)
      (Date December 13 2016)))
)
  (libparts
  (nets
    (net (code 1) (name A_TEMP)
      (node (ref U1) (pin 28))
      (node (ref U4) (pin 2)))
    (net (code 2) (name DATA)
      (node (ref D1) (pin 2))
      (node (ref J6) (pin 2))
      (node (ref U1) (pin 14))
      (node (ref U5) (pin 5)))
    (net (code 3) (name FSK)
      (node (ref U2) (pin 1))
      (node (ref U2) (pin 3))
      (node (ref U5) (pin 3)))
    (net (code 4) (name FSK_BUF)
      (node (ref C5) (pin 2))
      (node (ref U2) (pin 4))
      (node (ref U2) (pin 6)))
    (net (code 16) (name SDA)
      (node (ref J1) (pin 1))
      (node (ref J3) (pin 1))
      (node (ref J4) (pin 1))
      (node (ref R8) (pin 2))
      (node (ref U1) (pin 12)))
    (net (code 17) (name SIG1)
      (node (ref C5) (pin 1))
      (node (ref R3) (pin 2)))
    (net (code 18) (name SIG3)
      (node (ref U1) (pin 9))
      (node (ref U6) (pin 10)))
    (net (code 19) (name SIG4)
      (node (ref C1) (pin 2))
      (node (ref C2) (pin 2))
      (node (ref C3) (pin 1))
      (node (ref T1) (pin 2)))
))

Problem solved… nets section was in libparts section of netlist. Netlist now reads into PCBNew correctly.

Why do you have that “(libparts” right before the start of your nets section? When I generate netlists with skidl, I never have the libparts section in there.

Yes that was the problem, I removed the (libparts and works good now! thanks