i have been trying to design a pcb for quectel EC200u interfacing it with the stm32microcontroller. I have marked pins 116, 18, 81, 82, 117, 55 as not connected but in the pcb the rat nestis showing to connect these pins
Without any additional info it is hard to help. Post the project or screenshots at least.
hello,I have uploaded the same. thankyou
I’m with straubm. You give very little information, and without that it’s hard to help.
Update…
A screenshot appeared.
What did you do to:
Did you put a “No Connect” flag on them in the schematic, or did you something else? The problem originates in the schematic, that is what determines the netlist. In the PCB you only see the result.
Two possibilities:
- there are tiny track fragments inside the pad outlines that are connected to another net.
Making pads outline mode might show these - you have used the letter “x” on the pad as a label rather than using the no connect flag
Third possibility: schematic got NC flags, but then there was no F8 to sync PCB.
I have put a no connect flag to the schematic. I have also added a screenshot of the schematic showing reserved pins
hey, i have checked it many times. but i havent done either. I dont know where the problem lies
A no connect flag? Did you actually put a label called X? A no connect is not a label, but a special entity, created with the no connect icon or the shortcut key q.
A label called X would have the effect of joining all those pins together.
davidsrb already raised this scenario.
Post a zip of your project and we can say for sure.
Are these “reserved” pins stacked on top of each other the pins in question?
It is very difficult to determine problems with guesswork because of lack of information provided.
I’m assuming your problem is the “Reserved” pins.
By stacking pins on top of each other in the symbol, you have joined them together, hence, when the PCB is updated from the schematic, there will be ratlines.
You will have ratlines joining the GNDs together also.
To fix the problem, separate the pins in the schematic then update the PCB. I’d suggest doing the same with the GNDs and join them correctly with wires or labels.
EDIT: No where is it mentioned that the problem is with the “reserved” pins and the pin numbers stacked in the “Reserved” location are impossible to read.
The result of the lack of information just causes more angst for the OP as well as frustration for the members attempting to help.
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hey, It actually helped. I edited the schematic and individually joined the pins to the no connect.
I think that you mean “flagged”, not “joined”
Is it really necessary to do something with unused pins. I have left them open.
You get an ERC warning or error, it is safe to ignore these if you understand their cause
I find the “No Connect” crosses in KiCad a useful addition. When I’ve placed one, I know that I have thought about some pin and left it open on purpose, instead of either a schematic design that is not finished yet or some wire deleted accidentally.
The problem in this post was the pin stacking, which connects all stacked pins to each other. I am not a fan of pin stacking at all. I want to be able to find all pins on the schematic. If I see a PCB (for example during rework or repair) then I want to be able to find any pin back in the schematic.
In this case I would probably have made a separate “unit” for the “reserved pins” and put that somewhere in a corner of the schematic.
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