Rats Nest Incorrect Wiring



I have a schematic with a 8 pin SOIC with pins 1 and 3 connected and 2 and 4 connected.

On creating the PCB the ratnest indicates 1 and 2 are connected (representing what should be 1 and 3) and 3 and 4 are connected (representing what should be 2 and 4).

Is it the case that the ratnest isn’t foolproof? I’m new to PCBNew and was relying on it to draw the wires, but I’m worried it’s done this mistake elsewhere.




Post a screenshot of your schematic and of the result in pcb_new. (You might need to make two replies because new users are limited to one image per post.)

And make sure you have schematic and pcb_new in sync (export the netlist and import it in pcb_new just to be sure.)

And give us your kicad version details.


Like all software, KiCAD does exactly what you tell it to do. In most cases, what you tell it to do is what you want it to do. There are two common errors with the symptom you describe:

  • A drafting error in the schematic. A connection line touches some place where you don’t want it to touch.

  • An error in assigning footprints to the schematic symbols. A symbol may have the incorrect footprint pre-assigned. (This is possible, but uncommon considering the number of reviews and checks a symbol experiences before it is accepted into the official KiCAD library.) More commonly, the circuit designer may have assigned an incorrect footprint in the symbol’s “Properties”, or the designer may have assigned an incorrect footprint in “CvPCB”.

If that isn’t enough information to help you find the error, post at least a screenshot of the section of your schematic containing the affected IC. Posting the KiCAD schematic file would be more helpful but we understand about problems with proprietary information, etc.


p.s. - as a new Forum member, you are limited regarding attachments until you reach a certain level of activity (reading threads, submitting posts, etc). Some users circumvent this by submitting multiple replies, with an attachment on each.


Great minds think alike!



There is a rendering issue with the rats nest, overlapping lines don’t always show properly. If you use “Highlight Net”, it will show the pads that are in a net correctly…


I’m unable to post screenshots, I wanted to. I’ll try a few posts…




It is always possible to post a link to the screenshot on some cloud based service



Something does not add up. In your last screenshot the reference of the part is Q24. In your first it is Q3.

And what is the second screenshot about?


Q3 and Q24 is using the same chip, I lost the screenshot of Q3 and I’ve since updated the wiring in PCBnew. Q24 is still todo.

Screen 1: in eeschema
Screen 2: in library editor
Screen 3: in pcbnew.

Kicad 4.06


We need a screenshot of the part in eeschema and the corresponding part in pcb_new. (Also make the screenshot of a bit larger area)

If you show us Q3 in eeschema but Q24 in pcb_new we can’t help you.


Q27 (same chip).




There is a rendering issue with the rats nest, overlapping lines don’t always show properly. If you use “Highlight Net”, it will show the pads that are in a net correctly…


And the last one is Q27.

It is not possible to check if pins 3 and 4 are connected elsewhere on the schematic; nor is the last screenshot legible enough to tell if the same nets are assigned to the pins (it almost looks to be the case).

ON EDIT: ^^^^^That is wrong. A closer examination shows that pins 1 and 3 can not possibly be tied to anything else. I was trying to read the netlist, not the schematic when I first posted.


Q27 schematic top pins are connected left 2; right 2. Bottom pins are inside 2; right 2. On the layout: Top and bottom are both left 2; right 2 according to the rats nest lines.

I think that is the issue.


The circuit is sensitive, I can’t show any more of the schematic. Rest assured all pins are connected to other components. I switched to Q27 as it’s the only one I haven’t sorted in pcbnew yet.

HiGreg has explained the issue better than I have, there’s a mismatch between the pins. When I created the symbol I ordered the pins 2-1-3-4 as it made sense for the components purpose, but it seems to have confused pcbnew.

Or I’m missing something. I have assumed the mapping is accomplished via the pin number, in which case it should work.