I have a chip with 3 power pins that are connected by a fill. For some reason one pair of pins still has a ratline even though the connection is made. Even more baffilng is that at the bottom of the chip there are 3 more and they don’t have the problem.
I have this in other places too, where what appears to be a ratline happens even though the connection
is made by a fill with the correct node ID.
thanks
does it go away if you move the zone boundary down a little bit so that the center of the pad is inside?
YES!!! Many thanks! 
Yeah. The explanation is that KiCad doesn’t consider a network connection to a pad if the connecting copper doesn’t intersect the center (or insertion point for offset pads) of the pad. Just one of the quirks that one learns of this program.
Actually it seems to require more than just covering the center of the pad. It’s OK though I can see what to do.
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