I’m worried ill in my layout I will end up with some of the sections of the tracks that will not use the net classes rules. Is there a tool to quickly identify those sections to be reviewed? Is there a process that can be used to prevent it?
Run the DRC and click the Save button.
Then, open the saved file in a Text-editor and search for Track.
You’ll see the tracks and their related rule.
You could write some code to do something related…
Example of a saved report…
How does that help?
Your DRC report shows a lot of clearance violations, some silkscreen things and such.
As far as I know there is no check for verifying whether all segments of a net are set to their respective netclass width. It is also common that not all parts of a net are set to their netclass width. For example, it’s common to use wider tracks for power distribution and connections, but a track to a pull-up resistor of such a net does not need a wide track at all.
You can set tracks to use their netclass width with: PCB Editor / Edit / Set Track and Via Properties, but this is not a check, it is a (potential) change of the track widths. You can use this function for the check too, if you:
Set tracks (of a certain net, netclass, or selection, whatever) to the netclass width, and then run DRC. If this results in DRC violations, then it’s likely some of those tracks have become wider. If it makes a mess of things, you can use PCB Editor / File / Revert (So make sure to save before you do the modification) and then manually fix the trouble spots.
It may be possible to create a custom rule (In: PCB Editor / File / Board Setup / Design Rules / Custom Rules) to check this directly, but I do not know much about these custom rules.
The syntax help shows a track_width constraint that can be used to:
Checks the width of track and arc segments. An error will be generated for each segment that has a width below the min value (if specified) or above the max value (if specified).
So again, it does not directly check for netclass width, but you can use it to check for certain widths.
And last, I guess it’s possible to write a python script for this inside the PCB editor.
For the Folk’s who’ve been insisting that DRC is a sooo Important and berating me because I don’t use DRC, I’m surprised… and leave it there…
My posted Screenshot was Not intended as a Tutorial but, rather to show that DRC/ERC has the Ability to Inspect items of interest.
Naturally, it’s important for User to create the DRC Rules that he/she deems important.
Below shows my Quickly Done Rule and the DRC Report Result… The Rule, the Actual Values, Severity…
This is just silly.
DRC is not fool proof, nor can it do everything, but still it is a useful tool.
So you don’t use DRC, but you write DRC rules and post screenshots of them?
The rule (presumedly called TW) seems to be useful, and close to what OP asks. It’s more useful if you add it to your post 
I have been collecting some custom rules in a thread. It also has one for checking line width on silkscreen: Custom Design rules Examples - #3 by paulvdh
From looking through the syntax help, there is no direct way to extract the netclass width in a custom rule. This may be a good feature request. I guess it’s less than half an hour of work to add that to the custom rules system for someone with knowledge in that area.
It literally took me 1-Minute to create the Rule and the NetClass. It’s all right there in the Panel’s…, including the tutorial/examples.
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