Questions about creating an array, defining milling slots, and using Margin layer

I have a small board that has milled slots and mousebites for breakout. It is a kicad refresh of a board I did on eagle years ago and have had many produced, so this is not a question on the design.

What is the best way to create an array? In eagle I manually duplicated the design and created an array like this – I need to do the same in kicad:

Also, the slots, which are on the edge cuts layer, do not show on the kicad 3d viewer. The pcb looks like this:

However, when I look in the 3d viewer it does not show the slots and complains about a malformed edge layer. Does kicad not handle openings within a pcb edge cut boundary? I could move the rout slots to a milling layer if that works somehow, but I had a similar issue with v-scores, which the fab needed on the edge cut layer (else they might miss it) and kicad complained about the score line on the edge layer.

This is the 3d view (the rectangle edge cut is just arbitrary for this test) which does not show the milled slots:

Example below illustrates using Array. Naturally, you can make each PCB such as to mate with other PCB edges for a Break-Away product, if desired as well as doing most imaginable other things…

Thanks @BlackCoffee – I had not seen that tool before, and it makes it very easy!

As for the mill slots not showing up on 3d view, I guess I will just live with that.

As for the mill slots not showing up on 3d view, I guess I will just live with that.

Please No, don’t ignore that.
Kicad allows integrated slots on the board and if the slots don’t show up on your board and a message bar writes “malformed edge layer” than there is something wrong with that slots. And that may also affect the gerber output.
Most probably the DRC should also report this error.

So try to correct this:

  • all edgecuts-shapes must form a continous shape
  • lines/arcs must exactly connect start at the endpoint of the last line/arc
  • it’s not enough to check the lines visually, as the start/endpoints must match precisely to the last digit
  • sometimes some lne-segments are doubled (llocated on top of each other) - this is not allowed
  • if you have imported the slot-shape from a dxf-file: there could be import-problems with some bezier/arc-shapes
  • to correct the current board:
    • open a new test-board in a second kicad-window
    • activate the edgecuts-layer on the appearance panel, than use the “DIM”-mode
    • select the board-ooutline and copy to the test-board
    • check if 3D-view works
    • now select one edgecuts-shape after another and copy to the test-board
    • always check if the 3D-view works
    • at some point the 3D-view will complain - so the last copied shape was faulty.
    • now you could examine this shape closely and find the non-continous point in that shape

My KiCad (7.0.1) shows them :slight_smile:

My arcs are not 180°, but as I remember I probably snapped line ends or arc ends one on another.
These holes are defined in footprint, but I believe that the same defined at PCB level will also be shown correctly.

That probably mens that for KiCad your holes are not closed and because of it they are not shown.

That remind me that I planned to check if my holes in footprint are correctly shown in footprint 3D preview in V7 (in V6 they were wrongly interpreted) and if in V7 it is still wrong report it.

Oh, yeah, yeah, yeah @mf_ibfeew and @Piotr, it was indeed a problem with the milled arcs imported from the original eagle file (and probably non-coincident endpoints). I had used the primitive arc tools in eagle to create them years ago. So I have now re-created them with the primitive arc tools in kicad and all is well.


1 Like

'nuther question as I tweak this layout – drc errors I am getting related to the MARGIN.

I use the margin layer as a way to control ground plane boundaries, and it limits plane fills nicely. However, on this tight little board I am seeing DRC errors complaining about “Board edge clearance violation” and “Silkscreen clipped by board edge” problems. In Board-Setup I have Copper-to-edge-clearance set to 0, as I prefer to manually enforce a 0.5mm clearance (but occasionally allow copper to get closer on some connectors that I push closer to the edge). On this board I have all pads inside this 0.5mm boundary, and a circle on the Margin layer to keep planes where I want them. But I don’t really understand the DRC errors – it is as if it thinks the board edge is actually the Margin boundary, and not the edge cut boundary.

I am happy with the layout, and can ignore the drc, but it is always nice to get rid of drc errors and warnings by configuring settings properly. There are four errors where mousebite holes intersect the mill slots (I want it that way) and will ignore those four errs.

Perhaps I am using the margin inappropriately?

When I read (it was V4, but practically V3 documentation) about margin I didn’t understood what it is supposed to be so I didn’t used it.
Recently there was a thread at forum (but I don’t know how to search it) from which I got the conclusion that margin layer working changed on the way from V3 to V7 but I don’t know when.
So may be some new meaning/testing to margin was added on V6/V7 change.

… it is as if it thinks the board edge is actually the Margin boundary, and not the edge cut boundary.

Thats the way the margin-layer is working. Margin layer could be seen as additional edge.layer but without a real milling. So all constraints belonging to edge.cuts also affect the margin-layer:

  • silkscreen crossing this margin-shape
  • copper (tracks, pads, zone fills) with clearance to that margin-item
  • … ??
  • there is a small, subtle difference to edge.cuts-layer: items on the edge.cuts-layer are computed using the centerline (so linewidth is not important), while items on the margin-layer are using (for constraints / drc) their real contour and respecting the real linewidth.

The more powerful option is to use a rule area.

There are advantages/disadvantages to the use of the margin-layer (and rule areas):

  • simple drawing shapes (lines, arcs, circles) can be used (additional to polygone shapes)
  • these simple shapes can easily modified later on
  • affects all layers together
  • margin-items are not that much tunable - they use the all board-constraints for the drc
  • The rule areas as more powerful counterpart allow to enable/disable specific items (pads, tracks, zone fills), and can be restricted to specific layers
  • but rule areas are harder to draw (ok, in v7 one can use create rule area from selection, so that argument is loosing importance) and even more harder to modify later

I appreciate the clarification @mf_ibfeew
I think that using the margin for controlling my planes (and living with the drc errs) is perhaps not the best. It is good to know the margin is not centerline boundary. Rules are very powerful but seem like overkill to me. I think I will just revert to using copper-to-edge clearance and in the few cases where I push a connector closer to the edge, just live with that drc flag.

one additional trailing sentence (maybe for later readers):
don’t confuse custom Rules (from board setup–>constraints–>custom rules) with rule Areas (from right side toolbar).

  • custom rules: for advanced users, for most usecases you can think of. Needs special rule-syntax.
  • rule areas: for medium advanced users - draw a polygon and set “keep out from this area/polygone” for tracks/pads/vias/fills with a simple checkbox.
1 Like

A final couple of notes:
Drawing these curved mill arcs, and ensuring that endpoints were coincident, was a real pain-in-the-bahookie, however, it’s done once and then replicated. The array tool @BlackCoffee pointed out worked a treat. I just made a rectangular array and then offset columns with move-exactly. Then it was just a matter of adding fiducials and tooling holes to the frame and the array is ready for production. Here is a snip (with ratsnest off, since the nets are all common):

It turned out great – another great big thank you to the kicad devs for making my life easier:

Oh, also note that the array operation generates new reference designators (they need to be unique for pnp) so I hid the ref-des on the original unit and added silk text to match. So R1 is labeled R1 on all of them…


Worth mentioning (perhaps…)

PCB mfg’s have standard ability to ‘Tab’ each part on a sheet of multiple PCB’s. This enables them to place the Tabs as they see fit to help reduce wasted Cu and board materials. Tab widith (and Height settings) facilitate better ‘Break-Away’ by not tearing inner layer materials/cu.

When making the Array, you can Select whether or not to keep ref des as is or to create new for each item…

Quick example shows some 1mm wide tabs without reduced PCB thickness (usually I set thickness value to about 1/2 PCB thickness)

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.