Question of hierachy, BUS and global label

Hi. I am designing some schematic.

I checked, bus are not connected to my wish.
But I can’t find how fix my schematic.

I cant upload picture, I link my schematic.
–> LINK <–

I wish connect CONF_DATA0 in CONN and CONF_DATA0 in CONF.
But It is not connected. (rule checker marking unconnected).

How fix to connect both?

(Self Answer)

bus must named by [m…n] (not [m:n)
and all bus wire must label. (in Sheet:FPGA, CONF_DATA is not labeled).