Question about netclasses and track thicknesses

Hello,

I have a quick question. I would like to specify the thickness of the PCB tracks directly in the schematic editor. This is what I get.
However, I would like some tracks to be thicker than others.

A quick sketch is better than a long explanation.

Thank you in advance.

You have to break the nets and make the thicker and thinner parts different nets. Have a look at using NetTies.

image

Blue is high current 3mm track width, cyan is low current 0.3mm width . . . but all at the same 24V

The colors and line thicknesses only work on net classes, and thus on whole nets. To do what you want, you actively have to split the nets into sections, and this can be done with Net Ties. A net tie is a regular symbol, and thus also has a footprint. Footprints for net ties are just two pads connected together with some copper. So they do not cost anything in production, but they are still footprints that you have to place on the PCB. This is necessary because KiCad can not know where you want to split the nets without them.

You are talking about “PCB tracks”, but what we see here are schematic wires. I hope you yourself understand what you are talking about. You can choose PCB track segment width pretty freely and it doesn’t depend on the visual representation of the schematic.

Thank you very much !
It work fine now.

I agree this is a good solution but since a NetTie is a physical item on the PCB it comes with other considerations (im waiting for net-ties being able to be placed on inner layers).

An alternative would be to use a rule area around the chips in question and then use the DRC rules to permit necking of the track.

(rule “ADC Breakout”
(constraint clearance(min 0.15mm))
(constraint track_width (min 0.125mm) (opt 0.125mm))
(condition “A.intersectsArea(‘ADC_breakout’)”)
)

Rules are on my list of things to get my head round :wink: