Purposefully having two pads on top of each other for decoupling

Hi Kicad Forum!

Let’s suppose for the moment that I have to use an autorouter. I’m trying to make sure that when auto routing it routes properly for decoupling caps. I thought I had figured out a good way which was to create a new footprint which I call C_DECOUPLE that actually has three pads. It looks exactly like a standard 0603 cap footprint, except it has a third pad which is a duplicate of pad 2 and sits right on top of it.

My thinking was that I could say:
Pad 1: GND
Pad 2: VCC
Pad 3: Whatever pin I want to decouple

By doing this my hope was that it would keep the auto router from doing silly things like:

VCC -> PIN -> Cap’s VCC

which is technically valid according to the netlist but not what I want.

Unfortunately it looks like having pads 2 and 3 on top of each other prevents me from routing to either of them. My guess is that their keepout rules keep traces away?

Does anyone have any suggestions? Is there a way to say that a pad has no keepout zone, or that these two pads really are supposed to be on top of each other?


You are talking about the odd picofarad of capacitance, hardly useful below microwave frequencies

@gtaubman There is not really a need to control the order of which things are connected for decoupling, as long as you have a low-inductance path to the device VCC pin, the capacitor will be effective. In some ways it is actually better that VCC reaches the capacitor before the device’s pin, because it guarantees the shortest path is to the capacitor, therefore the lowest inductance. And when the device sources high-frequency current, it will sink from the capacitor first.

Thanks David and EE for the fast responses!

EE, I think what you’re suggesting is what I’m trying to achieve. The concern I have is that the pin doesn’t even need to be connected to the cap through any direct trace and the auto router will still be happy. The capacitor is still connected to VCC, so obviously there is a path between it and the pin, but it might be quite a meandering one.

For example in this image pin 24 was supposed to be connected to the cap below it, but after routing isn’t really decoupled at all, and all the other pins and caps are powered through pin 24.

If this is fine I’m totally happy not to worry about it!

Thanks again,

@gtaubman Ok… This looks pretty bad. Is that what the auto-router is giving you? I haven’t seen any good stuff coming out from those. Does not look that hard to route, why don’t you give it a shot yourself?
Prioritize VCC over GND. Your GND pins can be connected to vias and then use a ground fill on your board top and bottom layers, there is little chance to screw it up. You’ll free up paths for VCC and you will get your straight connection to the capacitors. Get that bottom-left corner cap closer to pin 24, no reason to be so far.

1 Like

Thanks again for the response!

Normally I’d be happy to route it myself, but this is a part of an automated system that I’m developing, hence the requirement to autoroute for now.

I’ll keep hunting around for a way to fool the auto router into doing the right thing for decoupling caps. Thanks again!

The layout you’re obtaining, regarding decoupling, is quite horrific. I mean, if you have low-frequency devices, it may well work fine (then again, in those cases it may well work fine even if you add no decoupling capacitors).

Long lines between the pins and the decoupling capacitors, and even worse, long lines from the capacitors to GND or VCC, is like a capital sin when it comes to decoupling. To make it worse, the lines are really thin (thus, higher inductance).

As a general recommendation, I would suggest you look up application notes on PCB design decoupling techniques and/or high-speed PCB design techniques (I can think of one good A.N. from Analog Devices, and one good A.N. from Texas Instruments on this subject).

More to the point of your post, a couple of possibly-crazy ideas that come to mind:

  • Net ties (maybe you can do your decoupling cap footprint with the same tricks the net-ties use)
  • Since the above really does not solve the issue of the undesired long trances to the capacitor, maybe you could design symbol and footprint for the IC, such that the decoupling capacitors are part of the IC itself (then, you can custom place the capacitors for each chip, following standard decoupling techniques).

Also: you could try to find a way to force the autorouter to set up a ground plane (if multi-layer, ground and power planes). If your circuit is such that decoupling is essential, then most likely a solid ground plane is also essential.

Autorouters have their limitations, which this example shows.
I have my own set of rules for routing:
1: for power, lay out a fixed grid manually.
2: route critical signal paths manually.
3: let the autorouter do the rest and optimize at the end if necessary.

Usually results in nice layouts. The fixed power grid and a sensible placing of the decoupling caps normally make the autorouter behave sensibly.

Thanks Cal! I think Net Ties are exactly what I was looking for. The trick of using graphic lines on the copper layer seems like it should do it. And yes if I can’t get that working I’ll definitely just make a mega component that has everything pre-placed. Thanks for both tips!!

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.