I have a 4 layer PCB, with two separate ground nets, and I want them to connect only at a through hole. I want the first ground on F.Cu and In1.Cu, and the second ground on B.Cu and In2.Cu.
I have created a footprint with three pads:
Pad 1 is a PTH, set to “connected layers only”.
An SMD Pad 2 of the same diameter on B.Cu
An SMD Pad 2 of the same diameter, manually edited to be on In2.Cu
I then use this footprint with a 2 pin net tie component in the schematic.
This appears to work but I get a “hole clearance violation” DRC errors between the SMD and PTH pads, and a “Padstack is questionable” warning on the edited SMD pad (fair enough).
Is there a way to do this that avoids the DRC errors or manual editing? Or is there a better way to achieve what I’m trying to do, which is to separate power and signal grounds and have them connected only at the through hole for the -ve power connection.
I am writing not because I have a great answer for you, but because I think your question is a perfectly good one which deserves some sort of answer. I suspect that nobody has answered you so far because nobody has a great answer, at least so far.
One thing: Please go to help>about>copy version info and paste it into your next post.
I have made and used my own net ties. A key is that it is a graphic bit of copper which (in a sneaky sort of way) connects two nets without announcing that to the KiCad software. I have made net ties in internal layers by text editing the file, to get around the fact that all of the “normal” net ties are on external layers.
I am not aware of any sort of via or plated through hole which is not intended as an electrical connection. I was thinking to have a via which connects only to a net tie on one layer or another, but even that might present issues. Of course any such work-around would probably also waste pcb area in a location where that may be tight.
I am hoping that my response might help raise the visibility of this thread and maybe prompt a better answer for you.
I can see some logic to this, but a few questions?
What net are intermediate layers seeing in the via?
Net Ties are typically used to ensure that two nets connect at one well defined location - eg Kelvin voltage sensing and ADC digital/analog grounds. Your via means that the two areas are already isolated, so having them the same net name still works.
I think perhaps I haven’t explained it properly. My goal is to have two separate grounds on different layers connected at just one location which is this PTH. The PTH is a actually a through-hole ground connection for the board rather than just a via. It will have a solid pin soldered into it.
I do need a net tie and separate nets, because if I had a single ground net, normal vias used elsewhere on the board will connect the supposedly separate ground planes.
From front to back, I want:
F.Cu - GND
In1.Cu - GND
In2.Cu - PGND
B.Cu - PGND
A PTH with “only connected layers” gets me the top two.
A co-located SMD pad on B.Cu gets me the bottom one (but with a DRC clearance warning), and a hand-edited SMD pad on In2.Cu gets me the last one, with more DRC warnings.
I do want an electrical connection, I just need different layers to be on different nets tied together by that connection.
When Googling this, I found some discussion of the support for putting SMD pads in inner layers, but it doesn’t look like it got implemented for v8.
Yes of course. We always want an electrical connection when we use a net tie. But our existing net ties use a graphical piece of copper which the software thinks is not intended as an electrical connection. We are sort of “fooling” the software. But SFAIK any sort of via is intended as an electrical connection. I do not know of something physically similar to a via which is not normally intended as an electrical connection.