the proportional footprint dimensioning concept developed by Rainer Taube and since 2021 included in IEC-61188-6-2:2021 seems to provide much better manufacturing yield than the IPC footprints, especially for small chip components.
Can anybody give me some hint how to change / use the existing library generator to create footprints according to this standard?
The footprint wizards are just Python scripts. Under “Messages” it shows you where the scripts are located. So simply pick one you like and modify it according to your needs.
I meant the scripted generation of whole families of components (from a table with the component dimensions), not the wizard to create one footprint a time manually.
I’m very interested about the topic of doing the best possible footprints. Can you share where did you read this information? I want to have a look at it myself.
Regards,
2nOrderEDO
There is a video in German: https://www.youtube.com/watch?v=sPcpI99RoDo and three PDF files at Veröffentlichungen / Berichte - Taube Electronic
There was a xls sheet IPC_FED_SMD_Reference_Calculator_20180629.xls available online, but it seems to be withdrawn now. FED or Taube might share it on request.
I might also be able to get access to IEC-61188-6-1:2021 and IEC-61188-6-2:2021 to retrieve relevant data from this standard.