Project critique

So I’m getting a bit closer in my project and wanted to see what the ‘brain trust’ thinks of the layout work.

I know it’s pretty amateurish work, but wanted to see if there were any ‘red flags’ that I need to go back and tweak before generating Gerbers and sending them off to a PCB house.

The connectors on the analog board are power, logic, and the process control loop (the messages are sent and received through this line). This has a ground plane to try and minimize interference with the adjacent logic board.

On the logic board, there’s the connector to the planned display board (redesign coming next to replace an ancient 8279 IC and 7-segment displays with something like an Arduino and a 2-wire LCD), power, analog connector, and status / configuration plugs.

FCT-II (99.6 KB)

It would be easiest to discuss if you’d attach screenshots of the layout.
This way you’ll get more feedback on the project.

The project is already attached and it’s even better for discussion, IMO. The layout is so large that one screenshot is difficult to follow.

@Meterman2026: you have deleted the symbol cache. Although you asked about the layout, it could help to see the schematic, too. It doesn’t work without the cache.

At least in the logic pcb you may have problematic +5V and GND. They seem to form loops. Is there a reason for not using zones for at least GND? It fills very nicely almost all the board because the layout is so loose and rigorously uses horizontal/vertical paradigm for the tracks. Here’s a screenshot with GND zone in the top and +5V in the bottom layer, the GND zone connects everything fully and +5V will be easy to connect by adding vias near pads. That would be a good start for better connections.

@eelik good point about the “Must have” ground plane.
The GND loops will definitely cause EMC issues.
Depending on what type of project is it, maybe it would be a good idea to go for a four-layer PCB and use continuous planes for GND and power, leaving two planes for H/V signal routes.
Otherwise, to get a good double-layer design with continuous groundplane will require a lot of work, starting with finding optimal placement for the components.

Close, but not the exact problem.
When I first open the schematic, it looks like:

When I view the properties of one of the [ ?? ] symbols, I see it references the Emetcon library, which is present in the project.

Eeschema / Preferences / Manage Symbol Libraries / Project Specific Libraries / "Add existing Library (icon) fixes it.

The links for project specific libraries are saved in the “sym-lib-table” file inside your project. Do not delete that file.
Even better: Never delete files of which you do not know the purpose.

Your schematic passes ERC without problems. That is good.

I always try to have high voltages in the top, and lower voltages in the bottom, and have signal flow from left to right. That does not work for the microprocessor, but it can work for the power supply.
For example, you have the power connector in the rightmost corner of the schematic and your decoupling capacitors rotated (and in two rows). The way you did it is not wrong, but keeping the top - down voltage flow and left - right signal flow makes the schematic easier to read and check, and thus the chance of errors smaller.

You have a bunch of long wires near your busses, with Reset, R/W, CLK, and some other signals. These are hard to follow. Working more with labels here is a good idea.

Connecting the 1MHz clock to the enable signals of the memory IC’s? Looks weird, but I am not very familiar anymore with these old IC’s.

Why use optocoupler U9 if you connect the “other” side to GND anyway?

No RAM IC? Does the HC11 have internal ram?

What is this thing supposed to do? Your MCHC11F1 has over 30 unused pins. Are these generic I/O? Maybe put connectors on these so it’s easier to use them for “something”. On the PCB it looks like a PLCC socket and the SMT parts are hard to reach.

Your PCB passes DRC with no errors, that is always a good thing.

Your power connector J1 is a regular 0.1" header. Use a better power connector here.

Your PCB is quite big with lots of space in between the parts. There is nothing wrong with this in itself. For the most part, the PCB will be a bit more expensive, but it’s also much easier to design and to route the tracks.

As Eelik already mentioned, the absence of a GND plane is quite bad. Adding a decent GND plane is the single most upgrade for this design. There is lots of documentation about GND planes and signal integrity. It is not an easy subject to grasp, but it is very important.

I appreciate the suggestion to go 4-layer and I will do so.

I’ll also remember to keep the sym-lib-table files as well.

As for the enable being driven by the clock, that’s what the original that I’m copying did…

The opto is an external ‘enable’ signal for the unit being operated by this device - the original used a comparator wired as a buffer. I wanted a bit more isolation for the ‘live’ side of the signal.

Yes, the HC11 has 1K of onboard RAM. It is a replacement for the original ‘custom’ MPU (an OEM version of the MC6800), so I really only need the HC11 for its instruction set and on-board RAM.

The RAM in the original consisted of a MC6810 SRAM at 0x0080 and a pair of HM-6561 NVRAM at 0x0C00, and trying to consolidate them without an extensive rewrite of the firmware was a headache solved by the presence of on-board RAM in the HC11 (and I was then able to simply adjust the upper RAM range down to 0x0100).

Yes I went with a PLCC socket just in case I somehow blow the MPU.

This is just my attempt to replicate an obscure piece of test equipment I’d come across just to say I did it. The original was part of a load management system.

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