Hello, I am attempting to connect a bus to the root sheet from a hierarchical sheet. I’ve created a simplified schematic to troubleshoot my error and experiencing the same issue. I believe I have read every related topic, and even bug reports, but banging my head for a couple of days now and I’m not getting it. I would appreciate some tips
Not shown here, but I have tried with bus connectors, and with net name local labels. It passes ERC when both buses are on the root sheet using local labels instead of hierarchical labels.
The Root sheet:
The sub sheet:
The ERC error report:
ERC report (3/12/2017 3:56:54 PM, Encoding UTF8 )
***** Sheet /
ErrType(2): Pin not connected (and no connect symbol found on this pin)
@ (111.76 mm,66.04 mm): Pin 2 (Passive) of component R2 is unconnected.
ErrType(2): Pin not connected (and no connect symbol found on this pin)
@ (111.76 mm,58.42 mm): Pin 2 (Passive) of component R1 is unconnected.
***** Sheet /Sheet58C4FFFB/
ErrType(2): Pin not connected (and no connect symbol found on this pin)
@ (71.12 mm,71.12 mm): Pin 2 (Passive) of component SW2 is unconnected.
ErrType(2): Pin not connected (and no connect symbol found on this pin)
@ (71.12 mm,62.23 mm): Pin 2 (Passive) of component SW1 is unconnected.
** ERC messages: 4 Errors 0 Warnings 4
Version info:
Application: kicad
Version: 4.0.5 release build
wxWidgets: Version 3.0.2 (debug,wchar_t,compiler with C++ ABI 1009,GCC 5.2.0,wx containers,compatible with 2.8)
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Boost version: 1.57.0
USE_WX_GRAPHICS_CONTEXT=OFF
USE_WX_OVERLAY=OFF
KICAD_SCRIPTING=ON
KICAD_SCRIPTING_MODULES=ON
KICAD_SCRIPTING_WXPYTHON=ON
USE_FP_LIB_TABLE=HARD_CODED_ON
BUILD_GITHUB_PLUGIN=ON
…and thank you KiCAD people for a great, open application without limitations!
Regards,
Darryl
Thanks for the quick reply Rene. I had tried that, and just did it again and still get the same result. Is there something I need to do to “refresh” the schematic after a change like this? I mean, besides saving it.
Hello ydohi, I wish it were that simple I tried renaming to SWX1? and get the same result. I recall at least one version of the manual uses an example where the hierarchical label is XYZ1, and the pin labels are XY-Z1 and it should work, but either way its not working for me.
I’ve haphazardly saved some custom parts, which I don’t want to lose but maybe I should try a later build to see what happens?
Update: I installed 4.0.6, recovered some edited components from cache. Fixed a typo, and made sure all labels were matched. It works! Thanks much everyone. I also edited my much more complex schematic to remove the hyphens and it worked there too! Pretty sure I had tried that before, but I’ve tried so many things now I’ve lost track.
What is most strange is that the net name local label on the bus is required in root, but not in the sub sheet. ERC fails the connections if the local label on the bus in the root is missing. It passes when the local label on the bus is on the root bus, and not on the sub sheet bus, like so:
Perhaps the example in the documentation should be changed to show a consistent local bus label to local pin labels. In fact, the example works when when the buses are on the same sheet, but fails when the pin labels appear as in the screen shot (with hyphens), and the local bus label is different (without hyphen) as in the text. This can complicates things when someone (like myself) makes silly assumptions about naming conventions when connecting buses between hierarchical sheets. Given, it does clearly state that one should use a common prefix.
From the 4.0.6 manual:
Something wrong at those document you see.
That picture you attached has 2 bus wires.
They must be named as PC-A[0…11] (or PC-A[0…19]?) and PC-DB[0…7].
Hyphen has no special meaning, but just a part of label.
See,“3.2. Bus connections in KiCad” section of Getting Started in KiCad
I am new user, then I couldn’t create multiple link. Then close once.
(It’s a troubled system.)
And I beleive bus wire has no functional meaning.
The node has a label is simply connect to other node has same label.
Following circuit outputs no ERC error, and U1pin2 connects to U1pin18, even the bus wire is given label as B[0…7]. https://www.dropbox.com/s/evplhp4nrvvcveh/bus.jpg?dl=0
(couldn’t upload pictures, then made link to Dropbox file. They will be broken link before long.)
Other hand, label on hierarchical port is the definition of signal to interface upper level.
In SUB sheet, label on hierarchical port connects to signal has same label.
If label is BUS, it is expanded to individual signals,
like as A[0…3] to A0, A1, A2, A3.
In UPPER sheet, hierarchical port name convert to connected wire/bus label.
… I I prepared another picture for you, but this site system allows no more post for new user.
Sorry, some time hope to discuss with you about this.
Same issue here. Busses are too much trouble. Since each wire needs a label anyway, just use a global label for each wire connection on your “bus”, like DRAM_ADR0, DRAM_ADR1 etc directy to the pin (no wire, no connector, just a label on the pin on each side), and be done with it. Global labels works and are easy to understand and reason about, unlike busses which nobody seems to be able to figure out. After trying everything and then some, the bus I was trying to make always said it has “no members” and never resulted in a connection - many hours wasted.
Well, apparently it can be done. As those people before you in 2017 had success, and I’ve also done it myself.
See for example this project (also on github)
I helped a bit there with the initial conversion from eagle -> KiCad.
But syntax is finicky. Note for example that ydohi uses three dots, while it should be two.
)
