Printing pcb to printer via size

If you have a via in your pcb and try to print it on a laser printer for home manufacturing, the size according to via definition is not mirrored on printout.
A via with size 1,6/0,8 gets printed with a hole approx. 0,9-1 mm wide.
This seems to apply only to via:s. Other components gets printed correctly.

I have seen in the code that there is a rounding that seems not to do what it’s supposed to do.

Please correct.
/Hans

I believe, but may be wrong that the specified VIA is finished size, leaving some fraction of a mm for plating

When MFG makes a via, they drill slightly larger and then plate (grow copper) on the hole to finished size, so for fabrication outputs the drill size is usually slightly larger than the finished hole. This is important because if you are soldering TH component, you care about finished size not drill size

As an aside, a related phenomenon is used to pull the soldermask back by a few fractions of a mm (defined in soldermask clearance) because the epoxy “spreads” by a few fractions of a mm when applied (but also sometimes explicitly needed for NSMD)

It gets more confusing when the PCB manufacturer tries to do some of this for you without informing you, usually benign changes don’t cause problems, but on occasion they can be major (like a pin not fitting in a hole), so it is important, IMO, to understand what the fabrication outputs tweak in order to satisfy the manufacturer.

Not certain which setting control this in the PDF output platting margin.

I think there is more to this now using a 0.8/0.4 via and a 0.4mm Trace (5.1.2 and 6.0.0)

When comparing a PDF Print

To a PDF Plot

The difference is noticable. The Hole gets a fixed size larger in print and is wider than the track, in the plot the track and the via are the same

EDIT: I have filed a bug on your behalf https://bugs.launchpad.net/kicad/+bug/1827686

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Yes, that is the standard. Specified hole sizes are the finished hole sizes. Plated holes will need to be drilled slightly larger to make up for the plating thickness.

Not quite. The fabrication outputs from PCB design software to the manufacturer is finished hole size. Different manufacturers (even different processes within the same manufacturer) have different through hole plating thicknesses. Unless the designer is doing a board with very specific specs, the designer doesn’t know nor needs to know what this plating thickness is. The manufacturer knows their plating thickness, so they will add twice that thickness to the customer’s specified drill size when actually choosing the bit to drill the holes with.

The print engine in KiCad is significantly less robust than the plot engine. I’ve up-voted your bug report.

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You are absolutely correct, I was trying to convey the concept you described and was innacurate, all holes specified to final via size is the only way I have built boards as well.

On the bug side, this behavior is controlled by the PSFineWidthAdjust which is accessible through the PostScript plotting interface, by varying the value I can see the ps drill size shrinking and expanding. I suspect this parameter in some default state is applied to print but is only configurable when plotting PS

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Thanks for these answers. I guessed that it must be a bug.

Before I order form Cogra Pro in Sweden I do manual manufacturing in my workshop. I print out the pcb on a matt OH-film and then use this film in a light box to expose the circuit board.

Approach so far has been to reduce via size to drill 0.6 to get it approx 0.8 at printout.

I’m glad you also noticed this behavior so it can be fixed.

Regards
Hans Röcklinger
RocIT HB
www.rocklinger.se

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Hi Hans,

Your workaround for the time being is to use the plot PDF output which does not have scaling of this kind and then print that PDF with other utility

Or you can use plot postscript output which you can control this scaling for the bleed ratio of your laser printer and print with external utility

This only affects direct “print” option

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Home manufacturing by printing a PCB on paper is not a good way to verify features at this scale.
How can you know that the output of your printer is the same as the input of your printer? I would not be surprised that part of the “Resolution enhancement” of your printer is adjusting the edges between black / white subtlety.
If you have a laser printer and your picture is transfered 1:1 to the static rolls in the printer, then there is still an analog process of wheter the toner sticks to the roll or not on the edges, and printers try to correct for such things, which is guesswork in the printer firmware.

The whole explanation about drilled hole size versus finised plated hole size is also not relevant in this context.

You are talking about “printed copper” features of the hole, while in real PCB manufacture the holes are usually drilled first before the copper is etched. The holes in the PCB appear nowhere in the Gerber files. There are no hole features in the copper. They simply do not exist in the Gerber file.

Hole size is only specified by the drill sizes in the excellon drill file. And as said before, manufacturers usually do some guesswork and use larger drills (which are also stronger) in an attempt to manufacture a finished hole in the size of what is specified in the drill file.

For home manufacturing it is also not usefull to have holes in the THT pads of the size of the finished drill. The best for hand drilling is a slight dimple in the center of the hole, just big enough to use as a guide to keep the drill centered.
If we assume an angle on the point of the drill of 120 degrees and a copper tickness of 35um then the etched hole in the copper should have a size of roughly
2sqrt(3) 35um, which is 121.24um.

If you etch a bigger hole into the copper before drilling, then the point of the drill touches the epoxy before the cutting edge of the point touches the copper, and the hole in the copper is not used as a guide anymore to center your drill.

In the hobby market there has been some software that takes a gerber file, and an excellon drill file and punches small drill starter holes in the pads. If you find (or write) such a program, the locations of your drilled holes will be more accurate.

On the other hand, If printer output for via hole size is different from pdf output, then it looks like a bug, and if reported properly it will very likely get fixed (according to some unspecified triage process). This is a user forum, and though some of the developers may also roam here, it is not the proper way to file bug reports.
Also remember that a lot of the development of KiCad is done by volunteers in their spare time.

The proper way to file a bug report is on Launchpad, and before you file a bug report there, you should first check if the same bug has already been mentioned by someone else. If it’s already mentioned, you can add the info you have, or file a new bug if it’s new.

Also, this implies you have a lot more knowledge about this bug:

Bravo for looking into the code and analysing it!
Things like that take time and effort.
But if you’ve found the location of this rounding error, you know in which file and in which line number it is. If you have analysed the rounding error, you probably have also thought of a better solution.

If you file a bug report, then a short explanation of why it is a rounding error, and how it can be corrected are usefull additions, and should be mentioned in the bug report (Along of course with a complete copy of your KiCad version from the “About” box).

A developer willing to put some time into fixing this buy may not have looked at that particular piece of code ever. That piece of code may have been unchanged for years.
Adding the info mentioned above will very much improve the likelyhood that it gets fixed fast, even if it is a very small and low priority bug.

A few months ago I made a bug report of a small error with an offset of pads in one of the footprint wizards, and it got fixed within a few days after reporting. The bug I’m writing about here was:
https://bugs.launchpad.net/kicad/+bug/1825261

Phew, a lot of typing for such a small thing.

Thank you for answering.

Before I used Eagle as tool and the same printer HP M552 and not paper but transparent OH-film (https://www.mattonbutiken.se/produkt/laser-kopierbar-ritfilm-a4?search=LASRITA4 in swedish) for transferring layout. This worked fine and a via of diameter 0,8 mm and outer diameter of 1,6 mm always had the correct size when measuring under microscope.

After developing circuit board I use Bungard Niten as via’s.

But Kicad 5.0 and 5.1 produces with the same prerequisites a hole that is approx 0,93mm when checking under microscope so something is definitely wrong (on the same printer and OH-film). If you check the same layout in the gerberview the via measures correctly.

Other pads and holes have correct size when printed, it’s just the via’s that gets wrong.

Currently I’m a developing period and have not much time to further investigate it, that have to wait.

Hans

PS with this method I can produce wires as thin as 0,15 mm isolated by 0,2 mm och ready board, not bad DS

To be honest i am a bit confused. Why would one want the copper free size to be equal to what the hole size should be? If you have any under etching you will have no copper near the hole. There is a reason why there is the option for “small drill mark” in the print dialog. This mark is there to allow centering of the drill. Having this mark already at the drill size will not even help with centering as the very tip of the drill is much smaller than the final size. (Again why would one want that?)

But if this option “print size = hole size” exists then it should definitely agree for all plated hole types. I suggest to raise a bug report.

I just made a little test PCB project.
I did not manage to reproduce a difference in hole size for the via versus pad holes, but report what I did anyway.

Made a project with A single shorted resistor, and used

Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P1.90mm_Vertical

as a footprint.

The pad properties of this footprint are 1.4mm pad with a 0.7mm hole (I did not change sizes:
image
and therefore I set:

Pcbnew / File / Board Setup / Design Rules / Net Classes / Via Drill

to 0.7mm, the same as the hole size for the THT pads.
Also set the “Via Size” outside diameter to 1.4mm, also the same as the THT pads, just to avoid perceived errors by optical illusion.

Then:

Pcbnew / File / Plot
and then plot to pdf with the “drill marks” set to “Actual Size”:
![image|690x286](upload://hqcjPnPHpdH1dcyxmt7Q6RpUpuv.png

A bunch of layers were printed / plotted to PDF and I looked at:
Holesize_Via_Print-B_Cu.pdf
by opening it in Inkscape.
At maximum zoom level the sizes of the holes were all the same size.
I am not proficient in Inkscape, so I measured the diameters of the holes by laying a (real life) steel ruler on my monitor, and the holes measured 182mm each. Via hole size is the same as the holes of the pads of the resistor.

I also did:

Pcbnew / File / Print

with “Drill marks:” as “Real drill”:

and then printed to a file, which generated the file “output.pdf”.
Opening the file in Inkscape again, I can zoom in much further, so far that the hole diameter is wider than my dual screen monitor setup, but all three holes measure the same again. There is a weird thing though:
The right pad of the resistor has a horizonal white line ( less than a pixel widht) over it:

2019-06-06_Holesize_Via_Print.zip (9.9 KB)

Just out of curiousity I then also plotted to a file with “small drill marks”
The holes are moticably smaller compared to the pad size, exactly as expected.
And as I explained in my lengty post above, this is a much better setting for home etching & drilling.
image

Application: kicad
Version: 5.1.0+dfsg1-1, release build
Libraries:
wxWidgets 3.0.4
libcurl/7.64.0 OpenSSL/1.1.1b zlib/1.2.11 libidn2/2.0.5 libpsl/0.20.2 (+libidn2/2.0.5) libssh2/1.8.0 nghttp2/1.36.0 librtmp/2.3
Platform: Linux 4.19.0-4-amd64 x86_64, 64 bit, Little endian, wxGTK
Build Info:
wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8) GTK+ 3.24
Boost: 1.67.0
OpenCASCADE Community Edition: 6.9.1
Curl: 7.64.0
Compiler: Clang 7.0.1 with C++ ABI 1002

Build settings:
USE_WX_GRAPHICS_CONTEXT=OFF
USE_WX_OVERLAY=ON
KICAD_SCRIPTING=ON
KICAD_SCRIPTING_MODULES=ON
KICAD_SCRIPTING_PYTHON3=ON
KICAD_SCRIPTING_WXPYTHON=ON
KICAD_SCRIPTING_WXPYTHON_PHOENIX=ON
KICAD_SCRIPTING_ACTION_MENU=ON
BUILD_GITHUB_PLUGIN=ON
KICAD_USE_OCE=ON
KICAD_USE_OCC=OFF
KICAD_SPICE=ON

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Thank you all for answering!

Look in the thread above from " crasic"
That’s what I have experienced.

I’ll to come back to this topic but right now I very busy with my new product.

Why would any one want the same size for a via when printing? I because I do at least 3-4 manual (circuit board development at home) tries before I go to the circuit board manufacturer to avoid a lot of extra cost. (unusual I guess that anyone does anything manual these days but I correct a lot of initial errors this way)

I place these “https://www.conrad.se/p/kontaktnitar-bungard-551678” in the via hole.

Hans

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