Is there a way in KiCad 6 PCB Editor to prevent DRC errors (Board Edge clearance violation) when using castellated holes?
@JeffYoung I would think we should not throw this if the fab attribute “castellated pad” is set, but it seems like we do. Any thoughts?
I wrote an FAQ article for this, Castellated edge; plated half holes in board edge, but it’s not up to date for v6. I was hoping the new custom drc rule system would help, but I didn’t find a way to do it so that it would simply work, and I gave up.
IMO a castellated pad should allow normal routing and zone filling when working, and suppress DRC errors. But this may not be as easy as it seems. For example a track or a zone should connect to a pad normally and the edge should not prevent it even near the pad, but yet the same zone/track/edge combination should throw an error farther away from the pad.
When that fab attribute was added it was just for output to Gerbers. Nothing else looks at it.
(But I agree that it would make sense to have other things look at it. Anyone care to log a bug?)
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