If you were using 5/5 trace/space design rules but couldn’t get a trace between some pins, what would be “better”:
In your experience/opinion, which violation would be less likely to cause a short between traces or an open trace? Do common process variations make one or the other less risky?
(Please don’t respond with: “You should never violate DRC. Reroute your board to avoid that.” Just don’t.)
What size is the pin ?
You did not mention the other choice, of reduce the pin size 
In extreme cases we have made special footprint parts, where the pins match the traces needing to go between them.
I’m already squeezing the pin pad pretty much. It’s a 14 mil hole and a 24 mil pad.
These issues are something I did some research on about a year back; fair warning in place as it has been some time.
It seemed like the copper was more difficult for the manufacturer’s to guarantee.
I’ve been reducing spacing on zones for the other layers, as small as 4 mill (and smaller) without issue (for which a popular prototype service DRC recommends 6mills).
Bottom line, I think it will depend on where you send the board files out to; but that the copper is, to them, the more important item to get right to qualify their boards.
I am curious what your outcome will be.
The rules don’t have to be integers. Sometimes a 5 mil track won’t fit but a 4.95 will
@davidsrsb But now you are talking about %tolerance of “copper track” for the Fab House.
As I stated above, it seemed to me that the copper layers had more issues with tight tolerances, than the other layers.
True. My own experience with 7/7 rules is that I sometimes see signs of rework clearing shorts.
I understand you are writing about one trace.
Reducing trace gives you 5+4+5=14. The equivalent reduction of space would be to 4.5 as 4.5+5+4.5=14.
Thanks for the replies. It’s a valid point that I can nudge my traces/spaces by sub-mil amounts. What I’m really looking for is which parameter is most sensitive to causing actual faults on the manufactured PCB.
@Sprig, you state early on that you’ve reduced spacing in zones from 6 to 4 mils without a problem. That seems to say that it’s less risky to violate spacing than it is trace width. Are you implying this only applies to copper-filled zones and wiring traces may be a separate case?
@davidsrsb, you seem to state the opposite, that shorts between traces are more of a problem (at least in your 7/7 process).
Thanks for your inputs. I realize there won’t be a definitive answer to this. I may just have to fab a small 1"x1" board and see what happens.
It is of course completely dependent on the quality of the fab where you want to manufacture your boards.
But 5 mills is getting a bit tight for a lot of manufacturers.
This document has sizes down to 3.5mil, but it also depends on copper thickness and (probably) also on what you are willing to pay extra.
https://www.eurocircuits.com/wp-content/uploads/EC-classification-ENGLISH-7-2017-V1.pdf
EC-classification-ENGLISH-7-2017-V1.pdf (209.3 KB)
I have no affiliation nor experience with eurocircuits, it was simply the first PCB house where I found some info about tracewidht etc.
Personally, I would maintain the track width and reduce the spacing. Depending on your fab it shouldn’t be an issue. In any case it is easier to remove copper than it is to try and put it back.
I am slowly preparing myself to use KiCad. I noticed thad KiCad footprints are rather designed in mm than in mils so I decided also switch my thinking from mils to mm (not easy). My experiments (I suppose it was KiCad 4.0.6 those time) showed me that if I have 0.6mm space between pads than I can’t route there 0,2mm track if sapcing is set to 0.2mm, but can route if any of this dimensions was 0.199. So I plan that when I seriously begin to use KiCad I will use spacings 0.001 less than rounded values and track with rounded (in mm) values.
Not really, but it may be a factor; it’s just what I have done without issue. I’ve been able to work my designs to have 100% copper fill on top and bottom.
Like I said, I did a Google about a year ago where I found some results where individuals had put different sized clearances, well below the design rules, I think from 10/10mill down in steps ending to 1/1mill on a section of their board.
It appeared to me that the copper was the hardest to keep in tolerance once it got below 4mills.
I’ve done 4 designs, for a total of 12 boards, that have a particular soldermask color, where some of the traces are as small as 6mill (usually try to stay at 10mill as this is still quite small), but the clearances are all set to 4mill and I’ve not had a single issue.
@davidsrsb May very well be correct if a different Fab house is used.
Certainly a good idea to run a test panel. Include tests in all orientations, and varying spaces.
When I have a choice of a slight rounding, I make the copper wider, as the finite-thickness of copper, means the trace edges etch very slightly along with the copper removal.
ie final trace size is always smaller than the exact film width.
2oz board has this effect more than 0.5oz board.
So this tends to agree with making the spaces narrower. The etching process will eat away at the copper sidewalls, leading to thinner traces and wider spaces, thus compensating for the initial, wider traces and narrower spaces.
Sometimes it’s good to take a step back and do a “sanity check”.
1mill is 0.001" and that is pretty dang small. In KiCad, with my monitor, I can zoom in and make a 10mill trace nearly 6" on the screen.
Grab a caliper or micrometer and set it to 1mill (0.001 in"), that is really friggen small.
@devbisme Thanks for the extra explanation; I didn’t bother spending more time pondering the issue.
I remember reading about this effect back when I was able to browse IPC documents (because my employer at that time had purchased them) at will. After a little google-fu I was able to determine a good google search term to read about this effect. Check out “copper etch undercut” for all the grisly details.
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