Thanks for the replies. It’s a valid point that I can nudge my traces/spaces by sub-mil amounts. What I’m really looking for is which parameter is most sensitive to causing actual faults on the manufactured PCB.
@Sprig, you state early on that you’ve reduced spacing in zones from 6 to 4 mils without a problem. That seems to say that it’s less risky to violate spacing than it is trace width. Are you implying this only applies to copper-filled zones and wiring traces may be a separate case?
@davidsrsb, you seem to state the opposite, that shorts between traces are more of a problem (at least in your 7/7 process).
Thanks for your inputs. I realize there won’t be a definitive answer to this. I may just have to fab a small 1"x1" board and see what happens.
I am slowly preparing myself to use KiCad. I noticed thad KiCad footprints are rather designed in mm than in mils so I decided also switch my thinking from mils to mm (not easy). My experiments (I suppose it was KiCad 4.0.6 those time) showed me that if I have 0.6mm space between pads than I can’t route there 0,2mm track if sapcing is set to 0.2mm, but can route if any of this dimensions was 0.199. So I plan that when I seriously begin to use KiCad I will use spacings 0.001 less than rounded values and track with rounded (in mm) values.
Not really, but it may be a factor; it’s just what I have done without issue. I’ve been able to work my designs to have 100% copper fill on top and bottom.
Like I said, I did a Google about a year ago where I found some results where individuals had put different sized clearances, well below the design rules, I think from 10/10mill down in steps ending to 1/1mill on a section of their board.
It appeared to me that the copper was the hardest to keep in tolerance once it got below 4mills.
I’ve done 4 designs, for a total of 12 boards, that have a particular soldermask color, where some of the traces are as small as 6mill (usually try to stay at 10mill as this is still quite small), but the clearances are all set to 4mill and I’ve not had a single issue.
@davidsrsb May very well be correct if a different Fab house is used.
Certainly a good idea to run a test panel. Include tests in all orientations, and varying spaces.
When I have a choice of a slight rounding, I make the copper wider, as the finite-thickness of copper, means the trace edges etch very slightly along with the copper removal.
ie final trace size is always smaller than the exact film width.
2oz board has this effect more than 0.5oz board.
So this tends to agree with making the spaces narrower. The etching process will eat away at the copper sidewalls, leading to thinner traces and wider spaces, thus compensating for the initial, wider traces and narrower spaces.
Sometimes it’s good to take a step back and do a “sanity check”.
1mill is 0.001" and that is pretty dang small. In KiCad, with my monitor, I can zoom in and make a 10mill trace nearly 6" on the screen.
Grab a caliper or micrometer and set it to 1mill (0.001 in"), that is really friggen small.
@devbisme Thanks for the extra explanation; I didn’t bother spending more time pondering the issue.
I remember reading about this effect back when I was able to browse IPC documents (because my employer at that time had purchased them) at will. After a little google-fu I was able to determine a good google search term to read about this effect. Check out “copper etch undercut” for all the grisly details.