Pre populated nets in libcms

pggood · November 20, 2015, 7:51pm

Im doing a board with an ATMEGA328P-A from the schematic library that uses a TQFP32 footprint. Ive connected VCC to pins 4 an 6 and GND to 21 5 and 3 the ratsnest in the PCB layout has a connection between

The rats nest ends up with a connection between 5,6,18 (GND,VCC,VCC) and a second 3,4,21 (GND,VCC GND)

Very bizzar and frustraiting

test.sch

EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
EELAYER 27 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title “”
Date “20 nov 2015”
Rev “”
Comp “”
Comment1 “”
Comment2 “”
Comment3 “”
Comment4 “”
$EndDescr
$Comp
L ATMEGA328P-A IC1
U 1 1 564F774C
P 6300 2750
F 0 “IC1” H 5550 4000 40 0000 L BNN
F 1 “ATMEGA328P-A” H 6700 1350 40 0000 L BNN
F 2 “TQFP32” H 6300 2750 30 0000 C CIN
F 3 “” H 6300 2750 60 0000 C CNN
1 6300 2750
1 0 0 -1
$EndComp
$Comp
L GND #PWR01
U 1 1 564F775D
P 5250 4000
F 0 “#PWR01” H 5250 3750 50 0001 C CNN
F 1 “GND” H 5250 3850 50 0000 C CNN
F 2 “” H 5250 4000 60 0000 C CNN
F 3 “” H 5250 4000 60 0000 C CNN
1 5250 4000
1 0 0 -1
$EndComp
Wire Wire Line
5400 3750 5400 3950
Connection ~ 5400 3850
Wire Wire Line
5400 3950 5250 3950
Wire Wire Line
5250 3950 5250 4000
$Comp
L VCC #PWR02
U 1 1 564F7786
P 5300 1650
F 0 “#PWR02” H 5300 1500 50 0001 C CNN
F 1 “VCC” H 5300 1800 50 0000 C CNN
F 2 “” H 5300 1650 60 0000 C CNN
F 3 “” H 5300 1650 60 0000 C CNN
1 5300 1650
0 -1 -1 0
$EndComp
Wire Wire Line
5300 1650 5400 1650
Wire Wire Line
5400 1650 5400 1950
Connection ~ 5400 1750
$EndSCHEMATC

test.net

(export (version D)
(design
(source C:\epirb\arduino\plb\plb\test\test.sch)
(date “11/21/2015 8:42:37 AM”)
(tool “eeschema (2013-07-07 BZR 4022)-stable”))
(components
(comp (ref IC1)
(value ATMEGA328P-A)
(footprint TQFP32)
(libsource (lib atmel) (part ATMEGA328P-A))
(sheetpath (names /) (tstamps /))
(tstamp 564F774C)))
(libparts
(libpart (lib atmel) (part ATMEGA168A-A)
(description “TQFP32, 16k Flash, 1kB SRAM, 512B EEPROM”)
(docs http://www.atmel.com/images/atmel-8271-8-bit-avr-microcontroller-atmega48a-48pa-88a-88pa-168a-168pa-328-328p_datasheet.pdf)
(fields
(field (name Reference) IC)
(field (name Value) ATMEGA168A-A)
(field (name Footprint) TQFP32))
(pins
(pin (num 1) (name “(PCINT19/OC2B/INT1)PD3”) (type BiDi))
(pin (num 2) (name “(PCINT20/XCK/T0)PD4”) (type BiDi))
(pin (num 3) (name GND) (type power_in))
(pin (num 4) (name VCC) (type power_in))
(pin (num 5) (name GND) (type power_in))
(pin (num 6) (name VCC) (type power_in))
(pin (num 7) (name “(PCINT6/XTAL1/TOSC1)PB6”) (type BiDi))
(pin (num 8) (name “(PCINT7/XTAL2/TOSC2)PB7”) (type BiDi))
(pin (num 9) (name “(PCINT21/OC0B/T1)PD5”) (type BiDi))
(pin (num 10) (name “(PCINT22/OC0A/AIN0)PD6”) (type BiDi))
(pin (num 11) (name “(PCINT23/AIN1)PD7”) (type BiDi))
(pin (num 12) (name “(PCINT0/CLKO/ICP1)PB0”) (type BiDi))
(pin (num 13) (name “(PCINT1/OC1A)PB1”) (type BiDi))
(pin (num 14) (name “(PCINT2/OC1B/~SS~)PB2”) (type BiDi))
(pin (num 15) (name “(PCINT3/OC2A/MOSI)PB3”) (type BiDi))
(pin (num 16) (name “(PCINT4/MISO)PB4”) (type BiDi))
(pin (num 17) (name “(PCINT5/SCK)PB5”) (type BiDi))
(pin (num 18) (name AVCC) (type power_in))
(pin (num 19) (name ADC6) (type input))
(pin (num 20) (name AREF) (type BiDi))
(pin (num 21) (name GND) (type power_in))
(pin (num 22) (name ADC7) (type input))
(pin (num 23) (name “(PCINT8/ADC0)PC0”) (type BiDi))
(pin (num 24) (name “(PCINT9/ADC1)PC1”) (type BiDi))
(pin (num 25) (name “(PCINT10/ADC2)PC2”) (type BiDi))
(pin (num 26) (name “(PCINT11/ADC3)PC3”) (type BiDi))
(pin (num 27) (name “(PCINT12/SDA/ADC4)PC4”) (type BiDi))
(pin (num 28) (name “(PCINT13/SCL/ADC5)PC5”) (type BiDi))
(pin (num 29) (name “(PCINT14/~RESET~)PC6”) (type BiDi))
(pin (num 30) (name “(PCINT16/RXD)PD0”) (type BiDi))
(pin (num 31) (name “(PCINT17/TXD)PD1”) (type BiDi))
(pin (num 32) (name “(PCINT18/INT0)PD2”) (type BiDi)))))
(libraries
(library (logical atmel)
(uri “C:\Program Files\KiCad\share\library\atmel.lib”)))
(nets
(net (code 1) (name “”)
(node (ref IC1) (pin 15)))
(net (code 2) (name “”)
(node (ref IC1) (pin 25)))
(net (code 3) (name “”)
(node (ref IC1) (pin 16)))
(net (code 4) (name “”)
(node (ref IC1) (pin 26)))
(net (code 5) (name “”)
(node (ref IC1) (pin 17)))
(net (code 6) (name “”)
(node (ref IC1) (pin 27)))
(net (code 7) (name “”)
(node (ref IC1) (pin 28)))
(net (code 8) (name “”)
(node (ref IC1) (pin 19)))
(net (code 9) (name “”)
(node (ref IC1) (pin 29)))
(net (code 10) (name “”)
(node (ref IC1) (pin 24)))
(net (code 11) (name “”)
(node (ref IC1) (pin 30)))
(net (code 12) (name “”)
(node (ref IC1) (pin 2)))
(net (code 13) (name GND)
(node (ref IC1) (pin 3))
(node (ref IC1) (pin 5))
(node (ref IC1) (pin 21)))
(net (code 14) (name VCC)
(node (ref IC1) (pin 6))
(node (ref IC1) (pin 4))
(node (ref IC1) (pin 18)))
(net (code 15) (name “”)
(node (ref IC1) (pin 7)))
(net (code 16) (name “”)
(node (ref IC1) (pin 8)))
(net (code 17) (name “”)
(node (ref IC1) (pin 9)))
(net (code 18) (name “”)
(node (ref IC1) (pin 10)))
(net (code 19) (name “”)
(node (ref IC1) (pin 20)))
(net (code 20) (name “”)
(node (ref IC1) (pin 1)))
(net (code 21) (name “”)
(node (ref IC1) (pin 11)))
(net (code 22) (name “”)
(node (ref IC1) (pin 31)))
(net (code 23) (name “”)
(node (ref IC1) (pin 12)))
(net (code 24) (name “”)
(node (ref IC1) (pin 22)))
(net (code 25) (name “”)
(node (ref IC1) (pin 32)))
(net (code 26) (name “”)
(node (ref IC1) (pin 13)))
(net (code 27) (name “”)
(node (ref IC1) (pin 23)))
(net (code 28) (name “”)
(node (ref IC1) (pin 14)))))

test.kicad_pcb

(kicad_pcb (version 3) (host pcbnew “(2013-07-07 BZR 4022)-stable”)

(general
(links 4)
(no_connects 4)
(area 0 0 0 0)
(thickness 1.6)
(drawings 0)
(tracks 0)
(zones 0)
(modules 1)
(nets 3)
)

(page A3)
(layers
(15 F.Cu signal)
(0 B.Cu signal)
(16 B.Adhes user)
(17 F.Adhes user)
(18 B.Paste user)
(19 F.Paste user)
(20 B.SilkS user)
(21 F.SilkS user)
(22 B.Mask user)
(23 F.Mask user)
(24 Dwgs.User user)
(25 Cmts.User user)
(26 Eco1.User user)
(27 Eco2.User user)
(28 Edge.Cuts user)
)

(setup
(last_trace_width 0.254)
(trace_clearance 0.254)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.254)
(segment_width 0.2)
(edge_width 0.1)
(via_size 0.889)
(via_drill 0.635)
(via_min_size 0.889)
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
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(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.5 1.5)
(pad_drill 0.6)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements FFFFFFBF)
(pcbplotparams
(layerselection 3178497)
(usegerberextensions true)
(excludeedgelayer true)
(linewidth 0.150000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotothertext true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory “”))
)

(net 0 “”)
(net 1 GND)
(net 2 VCC)

(net_class Default “This is the default net class.”
(clearance 0.254)
(trace_width 0.254)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
(add_net “”)
(add_net GND)
(add_net VCC)
)

(module TQFP32 (layer F.Cu) (tedit 43A670DA) (tstamp 564F781D)
(at 176.1 136.8)
(path /564F774C)
(fp_text reference IC1 (at 0 -1.27) (layer F.SilkS)
(effects (font (size 1.27 1.016) (thickness 0.2032)))
)
(fp_text value ATMEGA328P-A (at 0 1.905) (layer F.SilkS)
(effects (font (size 1.27 1.016) (thickness 0.2032)))
)
(fp_line (start 5.0292 2.7686) (end 3.8862 2.7686) (layer F.SilkS) (width 0.1524))
(fp_line (start 5.0292 -2.7686) (end 3.9116 -2.7686) (layer F.SilkS) (width 0.1524))
(fp_line (start 5.0292 2.7686) (end 5.0292 -2.7686) (layer F.SilkS) (width 0.1524))
(fp_line (start 2.794 3.9624) (end 2.794 5.0546) (layer F.SilkS) (width 0.1524))
(fp_line (start -2.8194 3.9878) (end -2.8194 5.0546) (layer F.SilkS) (width 0.1524))
(fp_line (start -2.8448 5.0546) (end 2.794 5.08) (layer F.SilkS) (width 0.1524))
(fp_line (start -2.794 -5.0292) (end 2.7178 -5.0546) (layer F.SilkS) (width 0.1524))
(fp_line (start -3.8862 -3.2766) (end -3.8862 3.9116) (layer F.SilkS) (width 0.1524))
(fp_line (start 2.7432 -5.0292) (end 2.7432 -3.9878) (layer F.SilkS) (width 0.1524))
(fp_line (start -3.2512 -3.8862) (end 3.81 -3.8862) (layer F.SilkS) (width 0.1524))
(fp_line (start 3.8608 3.937) (end 3.8608 -3.7846) (layer F.SilkS) (width 0.1524))
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(fp_line (start -5.0292 -2.8448) (end -5.0292 2.794) (layer F.SilkS) (width 0.1524))
(fp_line (start -5.0292 2.794) (end -3.8862 2.794) (layer F.SilkS) (width 0.1524))
(fp_line (start -3.87604 -3.302) (end -3.29184 -3.8862) (layer F.SilkS) (width 0.1524))
(fp_line (start -5.02412 -2.8448) (end -3.87604 -2.8448) (layer F.SilkS) (width 0.1524))
(fp_line (start -2.794 -3.8862) (end -2.794 -5.03428) (layer F.SilkS) (width 0.1524))
(fp_circle (center -2.83972 -2.86004) (end -2.43332 -2.60604) (layer F.SilkS) (width 0.1524))
(pad 8 smd rect (at -4.81584 2.77622) (size 1.99898 0.44958)
(layers F.Cu F.Paste F.Mask)
)
(pad 7 smd rect (at -4.81584 1.97612) (size 1.99898 0.44958)
(layers F.Cu F.Paste F.Mask)
)
(pad 6 smd rect (at -4.81584 1.17602) (size 1.99898 0.44958)
(layers F.Cu F.Paste F.Mask)
(net 2 VCC)
)
(pad 5 smd rect (at -4.81584 0.37592) (size 1.99898 0.44958)
(layers F.Cu F.Paste F.Mask)
(net 1 GND)
)
(pad 4 smd rect (at -4.81584 -0.42418) (size 1.99898 0.44958)
(layers F.Cu F.Paste F.Mask)
(net 2 VCC)
)
(pad 3 smd rect (at -4.81584 -1.22428) (size 1.99898 0.44958)
(layers F.Cu F.Paste F.Mask)
(net 1 GND)
)
(pad 2 smd rect (at -4.81584 -2.02438) (size 1.99898 0.44958)
(layers F.Cu F.Paste F.Mask)
)
(pad 1 smd rect (at -4.81584 -2.82448) (size 1.99898 0.44958)
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(pad 24 smd rect (at 4.7498 -2.8194) (size 1.99898 0.44958)
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(pad 18 smd rect (at 4.7498 1.9812) (size 1.99898 0.44958)
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(model smd/tqfp32.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

)

Joan_Sparky · November 21, 2015, 12:22am

I loaded your schematic and can’t see an error.

Your netlist looks alright too as the right pads are being bound together to the correct nets:

…
(net (code 13) (name GND)
(node (ref IC1) (pin 3))
(node (ref IC1) (pin 5))
(node (ref IC1) (pin 21)))
(net (code 14) (name VCC)
(node (ref IC1) (pin 6))
(node (ref IC1) (pin 4))
(node (ref IC1) (pin 18)))
…

So let’s go to pcbnew…

The version of KiCAD you seem to be using is not considered to be contemporary anymore… we’re at BZR63xx these days. A lot has changed (especially with footprints).
I would suggest you upgrade to something more recent. What OS you’re running KiCAD on?
For Windows you should be trying one of the recent builds (https://kicad.org/download/windows/) as the 4.0.0 RC2 has some problems/bugs as other have found.

Anyway, back to your 2013-stable output…
If I look at it in the default canvas (pcbnew > view > switch to …) I can see that the GND & VCC pads for 3,4,5,6 are vertically aligned over each other and when pcbnew is drawing ratsnests it has the bad trait to not to draw ratsnest lines that are right on top of each other… thus you get this:

Where as compared to OpenGL you probably wouldn’t have had worried at all

As you can see the TQFP footprint and the net names differ from the ones you have in your file (3V3 instead of VCC), so you see it’s no problem with your libraries. It’s happening in BZR6097 and I guess even in the latest in default canvas.

Conclusio - the default canvas (which will be dropped afaik - OpenGL is the one they will be using solely at some point) has some visualization shortages when it comes to draw ratsnest lines over each other, nothing fundamentally wrong.

PS: can you edit the title of this thread to something akin to the conclusio… ‘pcbnew default canvas ratsnest visual problem’? Thanks.