Power and Ground crossed


#1

I created a part for the Microchip PIC32MX360 here and all the VDD and VSS are power in types. After laying out the board I noticed some oddities and after doing a full audit I noticed that the nets had 3.3V and GND tied directly together even though the schematic has no ties. I put the part in its own schematic and tied all the power to one rail and all the ground to the other. I noticed that if I remove pin D5 that it no longer shorts to the power rail but even after recreating the D5 pin and then connecting it to ground it shorts the entire rail. Any idea from these pictures what I’m doing wrong?

You can see from the pictures the PCB showing the wrong NETs and then from the power schematic picture it looks right and the ground schematic picture also looks right. According to the PCB C2,D4,D5,E5 are one net and everything else is the other net. It appears from the PCB that D5 is tied to E5 and F5 is tied to G5 creating the shorts but the schematic has no defined connections for either of these.


#2

Here is the power schematic


#3

And then the ground schematic


#4

How do you know it ‘shorts the entire rail’ ?
The net names on those pins look fine, you may be confusing a rendering artifact - try partially route some traces, so the ratsnest do not overlap.

If you look at the PCB file in a text editor, do all the pins have the same net name ?


#5

They are connected. I slimmed down the original schematic to be able to show the problem as D5/E5 from picture one clearly has a network connection that shouldnt be there. F5/G5 are also directly connected,

The Netlist looks fine however starting the routes they clearly allow the pins to connect which shouldnt happen.


#6

I routed the rails except for the two connections creating the issues which should make it a little more clear.


#7

Try routing those final ones, so you do not have two ratsnets overlaid.


#8

Thanks for that. It appears cosmetic as it won’t let me route directly to them even though it appears to want to directly connect. If i create a via and go to the proper rail it works as expected.

Much appreciated.


#9

I think that display artifact is fixed in V5 - you could try the nightly builds to confirm that ?
The net-labels on the pins show the nets are indeed separate, even if the display is ‘strange’.


#10

I am waiting for the 5.0 release and had avoided the nightly build thinking stable was a better plan however I will try that.

Thanks again.


#11

I think the OpenGL canvas in 4.0.x doesn’t cause this problem either.
Try switching to it with [F11] (legacy is at [F9]) and see if that helps.
Should show those lines completely - without blanking them out if they overlap - less confusion.


#12

A simple trick to test if a wire is connected to a component properly is to drag a component. Hover your mouse above it and press ’ g ’
Connected wires will stay connected. Press [ Esc ] when you’re done and the component jumps back to it’s original positon.

Have you tried looking at the component library or netlist in a text editor? For possible errors there.
It’s all readable ASCII and the file formats are well documented The color scheme is a bit vague, but there is a link under specified in this PDF on the KiCad site.


#13

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